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Texas Instruments LM3S5G31

The Texas Instruments LM3S5G31 is an ARM Cortex-M3 Processor Core - 80-MHz operation; 100 DMIPS performance - ARM Cortex SysTick Timer - Nested Vectored Interrupt Controller (NVIC) On-Chip Memory - 384 KB single-cycle Flash memory up to 50 MHz; a prefetch buffer improves performance above 50 MHz - 64 KB single-cycle SRAM - Internal ROM loaded with StellarisWare software: External Peripheral Interface (EPI) - 8/16/32-bit dedicated parallel bus for external peripherals - Supports SDRAM, SRAM/Flash memory, FPGAs, CPLDs Advanced Serial Integration - CAN 2.0 A/B controller - USB 2.0 Device - Three UARTs with IrDA and ISO 7816 support (one UART with modem flow control and status) - Two I2C modules - Two Synchronous Serial Interface modules (SSI) System Integration - Direct Memory Access Controller (DMA) - System control and clocks including on-chip precision 16-MHz oscillator - Three 32-bit timers (up to six 16-bit) - Six Capture Compare PWM pins (CCP) - Lower-power battery-backed hibernation module - Real-Time Clock in Hibernation module - Two Watchdog Timers - Up to 67 GPIOs, depending on configuration Advanced Motion Control - Six advanced PWM outputs for motion and energy applications - Four fault inputs to promote low-latency shutdown - Two Quadrature Encoder Inputs (QEI) Analog - Two 12-bit Analog-to-Digital Converters (ADC) with 16 analog input channels and a sample rate of one million samples/second - Two analog comparators - 16 digital comparators - On-chip voltage regulator JTAG and ARM Serial Wire Debug (SWD) 100-pin LQFP package 108-ball BGA package Industrial (-40°C to 85°C) Temperature Range.

[Chip Vendor] [Distributors]

Development Tools
Compiler, Assembler, Linker, Debugger
JTAG Debuggers
Data Sheets
Data Sheet
6,809,410 bytes
Generic User Guide
1,364,135 bytes
Technical Reference Manual
2,247,922 bytes

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Header Files
FLASH Utilities
Device Programmers
Real-Time OS
Simulated Features
NOTE
Simulation for this device is provided by the default peripheral simulation driver.

Complete peripheral simulation is not available and is not planned to be implemented by ARM.

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