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PalmChip Palm8051

The PalmChip Palm8051 is an 8051 based CMOS controller core for SoC, with single clock instruction execution. This core supports : up to 8KBytes of On-chip Program Memory, and 256 bytes of On-chip Data RAM, up to 232KBytes external program memory, up to 64KBytes external data memory, Dual DPTR, wait state support for slow external peripherals, 32 I/O lines, 2 16-Bit Timers/Counters, 6 Interrupt sources with 2 Priority Levels, Full duplex serial port, and CoreFrame® SOC integration architecture.

[Chip Vendor] [Distributors]

Development Tools
Compiler, Assembler, Linker, Debugger
Header Files
Real-Time OS
Simulated Features

The following on-chip peripherals are simulated by the Keil Software µVision Debugger.

  • Interrupts 6S/4L (Including External)
  • Port 0
  • Port 1
  • Port 2
  • Port 3
  • Power save modes (Idle & Power down)
  • Serial UART (Enhanced Interface)
  • Timer 0
  • Timer 1
  • Timer 2 (Extended Timer 2)
  • X2 mode for CPU with Clock Control
AGSI Drivers

The following AGSI Drivers are available for the Keil Software µVision Simulator.

AGDI Drivers

The following AGDI Drivers are available for the Keil Software µVision Debugger.

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