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Atmel SAM3X8E

The Atmel SAM3X8E is a Core - ARM Cortex-M3 revision 2.0 running at up to 84 MHz - Memory Protection Unit (MPU) - Thumb-2 instruction set - 24-bit SysTick Counter - Nested Vector Interrupt Controller Memories - From 128 to 512 Kbytes embedded Flash, 128-bit wide access, memory accelerator, dual bank - From 32 to 100 Kbytes embedded SRAM with dual banks - 16 Kbytes ROM with embedded bootloader (UART, USB), IAP routines - Static Memory Controller (SMC): SRAM, NOR, NAND support. - SDRAM Controller System - Embedded voltage regulator for single supply operation - POR, BOD and Watchdog for safe reset - Quartz or ceramic resonator oscillators: 3 to 20 MHz main and optional low power 32.768 kHz for RTC or device clock. - High precision 8/12 MHz factory trimmed internal RC oscillator - Slow Clock Internal RC oscillator as permanent low-power mode device clock - PLL for device clock, PLL for USB 2.0 HS OTG - Temperature Sensor - Up to 17 peripheral DMA (PDC) channels and 6-chn. central DMA plus dedicated DMA for HS USB OTG and Ethernet MAC Low Power Modes - Sleep, Backup modes. - Backup domain: VDDBU pin, RTC, 8 32-bit backup registers - Ultra Low-power RTC Peripherals - USB 2.0 Device/Mini Host OTG - Up to 4 USARTs (ISO7816, IrDA, Flow Control, SPI, Manchester, LIN support) - UART - 2 TWI (I2C compatible), up to 6 SPIs, 1 SSC (I2S), 1 HSMCI (SDIO/SD/MMC) - 9-Chn. 32-bit Timer/Counter (TC) for capture, compare and PWM mode, Quadrature Decoder Logic and 2-bit Gray Up/Down Counter for Stepper Motor - Up to 8-chn. 16-bit PWM (PWMC) with Complementary Output, Fault Input, 12-bit Dead Time Generator Counter for Motor Control - 32-bit Real Time Timer (RTT) and RTC with calendar and alarm features - ADC (16-chn. 12-bit 1Msps) - DAC (2-chn. 12-bit 1 MSPS) - Ethernet MAC 10/100 (EMAC) - 2 CAN Controller - True Random Number Generator (TRNG) I/O - Up to 164 I/O lines - Up to 6 32-bit Parallel Input/Outputs.

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The following middleware components are pre-configured in MDK-Professional
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Simulated Features
Simulation for this device is provided by the default peripheral simulation driver.

Complete peripheral simulation is not available and is not planned to be implemented by ARM.

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