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Digital Core Design DR8051CPU
The Digital Core Design DR8051CPU is an 8051 based Pipelined High Performance Microcontroller IP Core with DoCD - DCD on-Chip Debugger. It is available for FPGA and ASIC usages as fully synchronous design with single clock domain. Its architecture is 7 times faster compared to legacy 80C51, area optimized, and low power. Main features and peripherals: up to 64 KB on-chip/off-chip CODE 256 Bytes on-chip RAM, 16 MB XDATA, PMU - Power Management Unit, CODE/XDATA Wait State feature, 2 Interrupts/2 priority levels,.
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