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Digital Core Design DR8051

The Digital Core Design DR8051 is an 8051 based Pipelined High Performance Microcontroller IP Core with DoCD - DCD on-Chip Debugger. It is available for FPGA and ASIC usages as fully synchronous design with single clock domain. Its architecture is 7 times faster compared to legacy 80C51, area optimized, and low power. Main features and peripherals: up to 64 KB on-chip/off-chip CODE, 256 Bytes on-chip RAM, 16 MB XDATA, PMU - Power Management Unit, CODE/XDATA Wait State feature, 32 I/O lines, 2 Timers/Counters, 5 Interrupts/2 priority levels, UART,.

[Chip Vendor]

Development Tools
Compiler, Assembler, Linker, Debugger
Data Sheets
Data Sheet for the Digital Core Design DR8051
Data Sheet
112,236 bytes
Instructions Set Details for the Digital Core Design DR8051
Instructions Set Details
261,793 bytes

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Header Files
Real-Time OS
Simulated Features

The following on-chip peripherals are simulated by the Keil Software µVision Debugger.

  • 4 Clocks per Machine Cycle
  • Clock Divider and Multiplier
  • External Memory Stretch Cycle support
  • Interrupts xS/2L (including external)
  • Port 0
  • Port 1
  • Port 2
  • Port 3
  • Power save modes (Idle & Power down)
  • Ring Oscillator
  • Timer 0
  • Timer 1
  • Timer Rate Control
  • Ultra High Speed (10 times faster)
AGSI Drivers

The following AGSI Drivers are available for the Keil Software µVision Simulator.

AGDI Drivers

The following AGDI Drivers are available for the Keil Software µVision Debugger.

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