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Digital Core Design DR80390XP

The Digital Core Design DR80390XP is an 80390/8051 based Pipelined High Performance Microcontroller IP Core with DoCD - DCD on-Chip Debugger. It is available for FPGA and ASIC usages as fully synchronous design with single clock domain. Its architecture is 7 times faster compared to legacy 80C51, area optimized, and low power. Main features and peripherals: up to 16 MB on-chip/off-chip CODE, 256 Bytes on-chip RAM, 16 MB XDATA, 8-bit stack pointer, PMU - Power Management Unit, CODE/XDATA Wait State feature, 2 DPTRs, CODE/XDATA Wait State feature, PMU - Power Management Unit, 15 Interrupts/2 priority levels, 32 I/O lines, 3 Timers/Counters, Watchdog timer, 2 UARTs, SPI - Serial Peripheral Interface, Master & Slave I2C, MDU - 16/32-bit Math Coprocessor, Floating Point Coprocessor,.

[Chip Vendor]

Development Tools
Compiler, Assembler, Linker, Debugger
Data Sheets
Data Sheet for the Digital Core Design DR80390XP
Data Sheet
135,621 bytes
Instructions Set Details for the Digital Core Design DR80390XP
Instructions Set Details
282,266 bytes

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Header Files
Real-Time OS
Simulated Features

The following on-chip peripherals are simulated by the Keil Software µVision Debugger.

  • 4 Clocks per Machine Cycle
  • Clock Divider and Multiplier
  • External Memory Stretch Cycle support
  • Interrupts xS/2L (including external)
  • Port 0
  • Port 1
  • Port 2
  • Port 3
  • Power save modes (Idle & Power down)
  • Ring Oscillator
  • Timer 0
  • Timer 1
  • Timer Rate Control
  • Ultra High Speed (10 times faster)
AGSI Drivers

The following AGSI Drivers are available for the Keil Software µVision Simulator.

AGDI Drivers

The following AGDI Drivers are available for the Keil Software µVision Debugger.

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