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Product Information Device Database® Downloads Compliance Testing Distributors |
Digital Core Design DP80390XPThe Digital Core Design DP80390XP is an 80390/8051 based Pipelined High Performance Microcontroller IP Core with DoCD - DCD on-Chip Debugger. It is available for FPGA and ASIC usages as fully synchronous design with single clock domain. Its architecture is 10 times faster compared to legacy 80C51. Main features and peripherals: up to 64 kB on-chip CODE, up to 16 MB off-chip CODE, 256 Bytes on-chip RAM, 16 MB XDATA, 8-bit stack pointer, PMU - Power Management Unit, CODE/XDATA Wait State feature, 2 DPTRs, CODE/XDATA Wait State feature, PMU - Power Management Unit, 15 Interrupts/2 priority levels, 32 I/O lines, 3 Timers/Counters, Watchdog timer, 2 UARTs, SPI - Serial Peripheral Interface, Master & Slave I2C, MDU - 16/32-bit Math Coprocessor, Floating Point Coprocessor,.
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