|
|||||||||||||||
Product Information Device Database® Downloads Compliance Testing Distributors |
Digital Core Design DP8051CPUThe Digital Core Design DP8051CPU is an 8051 based Pipelined High Performance Microcontroller IP Core with DoCD - DCD on-Chip Debugger. It is available for FPGA and ASIC usages as fully synchronous design with single clock domain. Its architecture is 10 times faster compared to legacy 80C51. Main features and peripherals: up to 64 KB on-chip CODE, up to 64 KB off-chip CODE, 256 Bytes on-chip RAM, 16 MB XDATA, PMU - Power Management Unit, CODE/XDATA Wait State feature, 2 Interrupts/2 priority levels,.
| ||||||||||||||
|
Arm’s Privacy Policy has been updated. By continuing to use our site, you consent to Arm’s Privacy Policy. Please review our Privacy Policy to learn more about our collection, use and transfers
of your data.