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Triscend TE512

The Triscend TE512 is an 8051-Based CSL Cells Controller with CSI System Bus, 2-Channel Advanced DMA Controler, Multi-Master Bus with Round-Robin Arbitration, Dual Data Pointers, 188 I/O Lines, 3 Timers/Counters, 12 Interrupt Sources / 3 Priority Levels, Watchdog Timer, 256 Bytes On-chip RAM, 32K Bytes On-chip XRAM.

*** IMPORTANT ***
Refer to Rochester Electronics at http://www.rocelec.com or to Zylogic at http://www.zylogic.com.cn.

*** EOL Notice ***
This device's End-Of-Life date is September 3, 2004.

[Chip Vendor]

Development Tools
Compiler, Assembler, Linker, Debugger
Data Sheets
Data Sheet for the Triscend TE512
Data Sheet
1,392,283 bytes

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Header Files
Example Code
Emulators
Real-Time OS
Simulated Features

The following on-chip peripherals are simulated by the Keil Software µVision Debugger.

The following on-chip peripherals are not simulated.

  • Configurable System Logic (CSL)
  • Dual DMA Controller
AGSI Drivers

The following AGSI Drivers are available for the Keil Software µVision Simulator.

AGDI Drivers

The following AGDI Drivers are available for the Keil Software µVision Debugger.


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