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Cadence Design Systems Inc. R8051

The Cadence Design Systems Inc. R8051 is a Single-clock 8051-compatible IP core with 8 times more performance than legacy 80C51 (with Dhrystone v1.1 Benchmark on identical clock speed). Features: 32 I/O lines, two 16-bit Timer/Counters, 5 interrupts/2 priority levels, dual data pointer, one serial peripheral interface, power management unit. Optional available: On-Chip Debug Support for Keil uVision Debugger. The R8051 IP core is compatible with FPGA and ASIC design.

*** EOL Notice ***
This device is no longer in production.

[Chip Vendor] [Distributors]

Development Tools
Compiler, Assembler, Linker, Debugger
Data Sheets
8051 Instruction Set Manual for the Cadence Design Systems Inc. R8051
8051 Instruction Set Manual
1,478,015 bytes

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Header Files
Emulators
Real-Time OS
Simulated Features

The following on-chip peripherals are simulated by the Keil Software µVision Debugger.

AGSI Drivers

The following AGSI Drivers are available for the Keil Software µVision Simulator.

AGDI Drivers

The following AGDI Drivers are available for the Keil Software µVision Debugger.


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