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Spansion MB9BF568R

The Spansion MB9BF568R is a 32bit ARM Cortex-M4F Core (r0p1) - Maximum clock frequency 160MHz - FPU built-in - Support DSP instruction Memory: - up to 1024kB Main Flash - 32kB Work Flash - up to 128kB RAM Base Timer: 8 channels(Max.) Watch counter CRC accelerator Multi-function Timer: 2 unit(Max.) - 16-bit free-run timer x3 channels/unit - Input capture x4 channels/unit - Output compare x6 channels/unit - A/D activation compare x6 channels/unit - Waveform generator x3 channels/unit - 16-bit PPG timer x3 channels/unit SD Card Interface: 1 unit QPRC: 2 channels(Max.) Dual Timer: 1 unit Watch dog Timer: 1 channel(SW) + 1 channel(HW) Multi-function Serial Interface: 8 channels(Max.) - Selectable from UART/CSIO/LIN/I2C External Bus Interface Real Time Clock: 1 unit DMA Controller: 8 channels DSTC: 128 channels USB2.0(Function/Host): 1 channel CAN: 2 channel(Max.) External Interrupt Controller Unit - Up to 16 external vectors - One non-maskable interrupt(NMI) 12-bit A/D Converter: Max. 24 channels(3 units) 12-bit D/A Converter: 2 channels(Max.) Low Power Mode Sleep, Timer, RTC, Deep standby RTC, Stop, Deep standby stop General Purpose I/O port MB9BF166M/F167M/F168M: 63(Max.) MB9BF166N/F167N/F168N: 80(Max.) MB9BF166R/F167R/F168R: 100(Max.) Built-in CR Debug - Serial Wire JTAG Debug Port (SWJ-DP) - Embedded Trace Macrocells(ETM) Low Voltage Detector Clock Super Visor Power Supply: 2.7V to 5.5V.

[Chip Vendor] [Distributors]

Development Tools
Compiler, Assembler, Linker, Debugger
JTAG Debuggers
Data Sheets
Data Sheet
2,348,306 bytes
Generic User Guide
1,755,988 bytes
Technical Reference Manual
935,507 bytes

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Header Files
FLASH Utilities
Real-Time OS
Simulated Features
NOTE
Simulation for this device is provided by the default peripheral simulation driver.

Complete peripheral simulation is not available and is not planned to be implemented by ARM.

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