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STMicroelectronics STM32L151CC

The STMicroelectronics STM32L151CC is an Operating conditions - Operating power supply range: 1.65 to 3.6 V (without BOR) 1.80 to 3.6 V (with BOR) - Temperature range: -40 to 85 °C Low power features - 7 modes - Dynamic core voltage scaling down to 233 uA/MHz - Ultralow leakage per I/O: 50 nA - Fast wakeup from Stop: 8 us - Three wakeup pins Core: ARM 32-bit Cortex-M3 CPU - 32 MHz maximum frequency, 33.3 DMIPS peak - Memory protection unit Reset and supply management - Low power, ultrasafe BOR - Ultralow power POR/PDR - Programmable voltage detector (PVD) Clock management - 1 to 24 MHz crystal oscillator - 32 kHz oscillator for RTC with calibration - Internal 16 MHz factory-trimmed RC - Internal 37 kHz low consumption RC - Internal multispeed low power RC, 64 kHz to 4 MHz - PLL for CPU clock and USB (48 MHz) Low power calendar RTC - Alarm, periodic wakeup from Stop/Standby Memories - 256 Kbyte Flash memory with ECC - 8 Kbyte of data EEPROM with ECC - 32 Kbytes of RAM Low Power Calendar RTC Up to 116 fast I/Os DMA: 12-channel DMA controller LCD 8 × 40 or 4 × 44 with step-up converter 2 operational amplifier 12-bit ADC up to 1 Msps/40 channels 2 × 12-bit DACs with output buffers 2 ultralow power comparators - Window mode and wakeup capability 11 timers: - 1 x 32-bit general-purpose timer - 6 × 16-bit general-purpose timers - 2 × 16-bit basic timers - 2 × watchdog timers (independent and window) Up to 12 communication interfaces - Up to 2 × I2C interfaces (SMBus/PMBus) - Up to 3 × USARTs (ISO 7816 interface, LIN, IrDA capability, modem control) - Up to 3 × SPIs (16 Mbit/s) - USB 2.0 full-speed interface up to 36 capacitive sensing channels 32-bit CRC calculation unit, 96-bit unique ID.

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Development Tools
Compiler, Assembler, Linker, Debugger
JTAG Debuggers
Data Sheets
Data Sheet
1,595,825 bytes
Generic User Guide
1,364,135 bytes
Reference Manual
28,147,336 bytes
Technical Reference Manual
2,247,922 bytes

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Header Files
FLASH Utilities
Real-Time OS
Simulated Features
NOTE
Simulation for this device is provided by the default peripheral simulation driver.

Complete peripheral simulation is not available and is not planned to be implemented by ARM.

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