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Spansion MB9AF121L

The Spansion MB9AF121L is a 32-bit ARM Cortex-M3 Core (r2p1) - Up to 40MHz Frequency Operation - Nested Vectored Interrupt Controller (NVIC) - 24-bit System timer (SysTick) On-chip Memories - Up to 128 Kbyte Flash - 8 Kbyte SRAM 32-bit ARM Cortex-M3 Core (r2p1) - Up to 40MHz Frequency Operation - Nested Vectored Interrupt Controller (NVIC) - 24-bit System timer (SysTick) On-chip Memories - 64 Kbyte Flash - 4 Kbyte SRAM Multi-function Serial Interface (Max. 8channels) - UART, CSIO, LIN, I2C A/D Converter (Max 8channels) - 12-bit A/D Converter - Priority conversion available (priority at 2levels) D/A Converter (Max 1channel) - 10-bit resolution Base Timer (Max. 8channels) - Operation mode: 16-bit PWM, 16-bit PPG, 16/32-bit reload, 16/32-bit PWC General Purpose I/O Port - Up to 51 fast general purpose I/O Ports - Some pins are 5V tolerant I/O Dual Timer (32/16-bit Down Counter) - 2 programmable 32/16-bit down counters Multi-function Timer - 16-bit free-run timer x 3ch. - Input capture x 3ch. - Output compare x 6ch. - A/D activating compare x 3ch. - Waveform generator x 3ch. - 16-bit PPG timer x 3ch. Real-time clock (RTC) External Interrupt Controller Unit - Up to 19 external interrupt input pins - Include one non-maskable interrupt (NMI) input pin Watchdog Timer (2channels) Clock and Reset - 5 clock sources (2 ext. osc, 2 built-in CR osc, and Main PLL) - Reset sources: INITX Pins, POR, SW, Watchdog, LVD, CSV Clock Super Visor (CSV) - Ext. OSC clock failure (clock stop) detect - Ext. OSC frequency anomaly detect Low Voltage Detector (LVD) - LVD1: error reporting via interrupt - LVD2: auto-reset operation Low-Power Consumption Mode - 4 power saving modes (SLEEP, TIMER, RTC, STOP) Debug - Serial Wire JTAG Debug Port (SWJ-DP) Unique ID (41-bit).

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Development Tools
Compiler, Assembler, Linker, Debugger
JTAG Debuggers
Data Sheets
Datasheet
1,247,633 bytes
Generic User Guide
1,364,135 bytes
Technical Reference Manual
1,106,603 bytes

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Header Files
FLASH Utilities
Real-Time OS
Simulated Features
NOTE
Simulation for this device is provided by the default peripheral simulation driver.

Complete peripheral simulation is not available and is not planned to be implemented by ARM.

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