Keil Logo

STMicroelectronics STM32F031K4

The STMicroelectronics STM32F031K4 is an Operating conditions - Voltage range: 2.0 V to 3.6 V core - ARM 32-bit Cortex-M0 CPU (48 MHz max) Memories - 16 to 32 Kbytes of Flash memory - 4 Kbytes of SRAM with HW parity checking CRC calculation unit Clock management - 4 to 32 MHz crystal osc. - 32 kHz osc. for RTC with calibration - Internal 8 MHz RC with x6 PLL option - Internal 32 kHz RC osc. Calendar RTC with alarm and periodic wakeup from Stop/Standby Reset and supply management - Power-on/Power down reset (POR/PDR) - Programmable voltage detector (PVD) Low power Sleep, Stop, and Standby modes VBAT supply for RTC and backup registers 5-channel DMA controller 1 × 12-bit, 1.0 us ADC (up to 16 channels) - Conversion range: 0 to 3.6V - Separate analog supply from 2.4 up to 3.6 Up to 39 fast I/Os - All mappable on external interrupt vectors - Up to 25 I/Os with 5 V tolerant capability 96-bit unique ID Up to 9 timers - One 16-bit 7-channel advanced-control timer for 6 channels PWM output, with deadtime generation and emergency stop - One 32-bit and one 16-bit timer, with up to 4 IC/OC, usable for IR control decoding - One 16-bit timer, with 2 IC/OC, 1 OCN, deadtime generation and emergency stop - one 16-bit timers, each with IC/OC and OCN, deadtime generation, emergency stop and modulator gate for IR control - One 16-bit timer with 1 IC/OC - Independent and system watchdog timers - SysTick timer: 24-bit downcounter Communication interfaces - one I2C interfaces - one USARTs supporting master synchronous SPI and modem control - one (18 Mbit/s) with 4 to 16 programmable bit frame Serial wire debug (SWD).

[Distributors]

Development Tools
Compiler, Assembler, Linker, Debugger
JTAG Debuggers
Data Sheets
Data Sheet
1,123,331 bytes
Generic User Guide
953,546 bytes
Reference Manual
10,836,500 bytes
Technical Reference Manual
472,236 bytes

Get Adobe Acrobat Reader

Header Files
FLASH Utilities
Device Programmers
Real-Time OS
Simulated Features
NOTE
Simulation for this device is provided by the default peripheral simulation driver.

Complete peripheral simulation is not available and is not planned to be implemented by ARM.

  Arm logo
Important information

This site uses cookies to store information on your computer. By continuing to use our site, you consent to our cookies.

Change Settings

Privacy Policy Update

Arm’s Privacy Policy has been updated. By continuing to use our site, you consent to Arm’s Privacy Policy. Please review our Privacy Policy to learn more about our collection, use and transfers
of your data.