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Spansion MB9BF416S

The Spansion MB9BF416S is a 32-bit ARM Cortex-M3 Core (r2p1) - Up to 144MHz Frequency Operation - Memory Protection Unit (MPU) - Integrated Nested Vectored Interrupt Controller (NVIC) - 24-bit System timer (Sys Tick) On-chip Memories - Up to 1 Mbyte Flash - Up to 64 Kbyte SRAM for high-performance CPU - Up to 64 Kbyte SRAM for CPU/DMA Controller External Bus Interface - Supports SRAM, NOR& NAND Flash device - Up to 8 chip selects - 8/16-bit Data width - Up to 25-bit Address bit CAN Interface (Max. 2channels) - Compatible with CAN Specification 2.0A/B - Maximum transfer rate: 1 Mbps Multi-function Serial Interface (Max 8channels) - UART, CSIO, LIN, I2C DMA Controller (8channels) A/D Converter (Max 32channels) Base Timer (Max 16channels) - Operation mode: 16-bit PWM, 16-bit PPG, 16/32-bit reload, 16/32-bit PWC General Purpose I/O Port - Up 154 fast I/O Ports Multi-function Timer (Max 3units) Quadrature Position/Revolution Counter (QPRC) (Max 3channels) Dual Timer (32/16bit Down Counter) Watch Counter External Interrupt Controller Unit - Up to 32 external vectors - Include non-maskable interrupt (NMI) Watch dog Timer (2channels) CRC (Cyclic Redundancy Check) Accelerator Clock and Reset - 5 clock sources (2 ext. osc, 2 CR osc, and PLL) - Reset sources: INITX Pins, POR, SW, Watchdog, LVD, CSV Clock Super Visor (CSV) - Ext. OSC clock failure (clock stop) detect - Ext. OSC frequency anomaly detect Low Voltage Detector (LVD) - LVD1: error reporting via interrupt - LVD2: auto-reset operation Low Power Mode - Three power saving modes (SLEEP, TIMER, STOP) Debug - Serial Wire JTAG Debug Port (SWJ-DP) - Embedded Trace Macrocells (ETM).

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Development Tools
Compiler, Assembler, Linker, Debugger
Evaluation Boards
JTAG Debuggers
Data Sheets
Data Sheet
1,278,167 bytes
Generic User Guide
1,364,135 bytes
Technical Reference Manual
1,106,603 bytes

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Header Files
FLASH Utilities
Real-Time OS
Simulated Features
NOTE
Simulation for this device is provided by the default peripheral simulation driver.

Complete peripheral simulation is not available and is not planned to be implemented by ARM.

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