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Holtek HT32F1251

The Holtek HT32F1251 is an ARM Cortex-M3 processor - Up to 72 MHz operation frequency - Nested Vectored Interrupt Controller (NVIC) - 24-bit SysTick timer On-chip memory - 8 KB on-chip Flash Memory with Flash Memory Accelerator - 1 KB Flash Option Byte - 2 KB on-chip SRAM - Flexible booting mode supports bootloader Flash Memory Controller - Flash accelerator to obtain maximum efficiency - 32-bit word programming (ISP and IAP) - Flash protection capability to prevent illegal access Power supply, reset, and clocks - Single 3.3 V power supply (2.7 V to 3.6 V) - Built-in 1.8 V LDO regulator for core and peripherals - Supply supervisor (POR, BOD, LVD) - External 4 to 16 MHz crystal oscillator - External 32,768 Hz crystal oscillator - Internal 8 MHz RC oscillator - Internal 32 kHz RC oscillator - On-chip PLL for system clock Power management - 4 power saving modes (Sleep, Deep-Sleep 1, Deep-Sleep 2, Power-Down) - Independent clock gating bits for each peripherals - VBAT battery power supply for RTC and backup registers ADC - 12-bit SAR ADC engine - Up to 1 Msps conversion rate - 8 external analog input channels - 2.7 V ~ 3.6 V conversion range Analog Operational Amplifier/Comparator - 2 x Operational Amplifier or 2 x Comparator function - Supply voltage range: 2.7 V ~ 3.6 V IO ports - Up to 32 GPIOs - Port A and Port B are mapped on 16 ext. interrupts (EXTI) - Almost all IOs are 5 V-tolerant except analog inputs Timers - 2 x 16-bit General-Purpose Timer (GPTM) with input capture or compare output function - 1 x Watchdog timer - 1 x Real Time Clock Communication interfaces - 1 x I2C interface, support both master and slave mode, up to 400 kHz - 1 x SPI interface, support both master and slave mode, up to 18 MHz - 1 x USART interface, up to 4.5 MHz Debug support - Serial Wire Debug Port (SW-DP) - 1-bit asynchronous trace (TRACESWO).

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Development Tools
Compiler, Assembler, Linker, Debugger
Evaluation Boards
JTAG Debuggers
Data Sheets
Data Sheet
767,143 bytes
Generic User Guide
1,364,135 bytes
Technical Reference Manual
1,106,603 bytes

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Header Files
FLASH Utilities
Real-Time OS
Simulated Features
NOTE
Simulation for this device is provided by the default peripheral simulation driver.

Complete peripheral simulation is not available and is not planned to be implemented by ARM.

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