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NXP (founded by Philips) LPC1227/301

The NXP (founded by Philips) LPC1227/301 is an ARM Cortex-M0 processor: - running at frequencies of up to 45 MHz (one wait state from Flash). up to 30 MHz (zero wait state from Flash). - Nested Vectored Interrupt Controller (NVIC). - Serial Wire Debug and Serial Wire Trace port. - System tick timer. Memory: - Up to 128 kB on-chip Flash (ISP and IAP via on-chip bootloader software). - Up to 8 on-chip SRAM. - Includes ROM-based 32-bit integer division routines. Clock generation unit: - crystal oscillator (operating range of 1 MHz to 25 MHz). - 12 MHz Internal RC oscillator (IRC). - PLL allows CPU operation up to the maximum CPU rate. - Clock output function that can reflect various clocks. - Real-time clock. Digital peripherals: - Micro DMA controller with 21 channels. - CRC engine. - Two UARTs (One UART with RS-485 and modem support and one standard UART with IrDA). - SSP/SPI controller. - I2C-bus interface. - Programmable high-current output drivers (16 mA) on four pins. - Up to 55 General Purpose I/O (GPIO) pins . - All GPIO pins can be used as edge and level sensitive interrupt sources. - Four general purpose counter/timers. - Windowed Watchdog Timer (WDT). Analog peripherals: - one 8-channel, 10-bit ADC. - Two analog comparators. Power: - Three reduced power modes: Sleep, Deep-sleep, and Deep power-down. - Processor wake-up from Deep-sleep mode via 12 port pins or peripheral interrupts. - Brownout detect with three separate thresholds each for interrupt and forced reset. - Power-On Reset (POR). - Integrated PMU (Power Management Unit). Single 3.3 V power supply (3.0 V to 3.6 V). Available as 64-pin and 48-pin LQFP package.

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Evaluation Boards
Data Sheets
Data Sheet
1,575,443 bytes
Errata Sheet
38,774 bytes
Generic User Guide
953,546 bytes
Technical Reference Manual
472,236 bytes
User Manual
2,845,022 bytes

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Header Files
FLASH Utilities
Device Programmers
Simulated Features
NOTE
Simulation for this device is provided by the default peripheral simulation driver.

Complete peripheral simulation is not available and is not planned to be implemented by ARM.

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