Device Database®

Microsemi A2F500M3G

The Microsemi A2F500M3G is a Microcontroller Subsystem (MSS) 100 MHz 32-Bit ARM Cortex-M3 1.25 DMIPS/MHz - Memory Protection Unit (MPU) - Single Cycle Multiplication, Hardware Divide - JTAG Debug, Serial Wire Debug and Single Wire Viewer Interfaces Internal Memory - Embedded Flash Memory (eNVM), 64 Kbytes to 512 Kbytes - Embedded High-Speed SRAM (eSRAM), 16 Kbytes to 64 Kbytes Multi-Layer AHB Communications Matrix - Provides up to 16 Gbps of On-Chip Memory Bandwidth 10/100 Ethernet MAC with RMII Interface2 Programmable External Memory Controller, Two I2C Peripherals Two 16550 Compatible UARTs Two SPI Peripherals Two 32-Bit Timers 32-Bit Watchdog Timer 8-Channel DMA Controller Clock Sources - 1.5 MHz to 20 MHz Main Oscillator - Battery-Backed 32 KHz Low-Power Oscillator with Real-Time Counter (RTC) - 100 MHz Embedded RC Oscillator; 1% Accurate - Embedded PLL with 4 Output Phases High-Performance FPGA Based on Actel's proven ProASIC FPGA Fabric Advanced 130-nm, 7-Layer Metal, Flash-Based CMOS Process Nonvolatile, Retains Program when Powered Off 350 MHz System Performance Embedded SRAMs and FIFOs - Variable Aspect Ratio 4,608-Bit SRAM Blocks - x1, x2, x4, x9, and x18 Organizations - True Dual-Port SRAM (excluding x18) - Programmable Embedded FIFO Control Logic Secure ISP with 128-Bit AES via JTAG FlashLock to Secure FPGA Contents Five Clock Conditioning Circuits (CCCs) with up to 2 Integrated Analog PLLs - Phase Shift, Multiply/Divide, and Delay Capabilities - Frequency: Input 1.5–350 MHz, Output 0.75 to 350 MHz Analog Front-End (AFE) Up to Three 12-Bit SAR ADCs - 500 Ksps in 12-Bit Mode - 600 Ksps in 8- and 10-Bit Mode Internal 2.56 V Reference or Optional External Reference One First-Order DAC (sigma-delta) per ADC - 12-Bit 500 Ksps Update Rate Up to 5 High-Performance Analog Signal Conditioning Blocks (SCB) per Device - T.