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Microsemi COREMP7

The Microsemi COREMP7 is a The CoreMP7 is fully compatible with the ARM7TDMI-S 32-bit processor from ARM. The CoreMP7 is supplied with an MP7Bridge for interfacing to an Advanced High-Performance Bus (AHB) based bus system. The ARM7TMDI-S core is an 32/16 bit RISC architecture, based on 32-bit ARMv4T instruction set, and 16-bit Thumb instruction set. It incudes an 32-bit ALU, 3-stage pipeline, a 32-bit external bus interface and an embedded real-time debug and JTAG interface. This core is optimized for Actel flash-based M7 devices and implemented fully in the fabric.

[Chip Vendor] [Distributors]

Development Tools
Compiler, Assembler, Linker, Debugger
Evaluation Boards
JTAG Debuggers
Data Sheets
Actel Data Sheet
265,509 bytes
Actel User Guide for the Microsemi COREMP7
Actel User Guide
1,099,431 bytes
ARM7TDMI-S Technical Reference Manual
1,477,711 bytes

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FLASH Utilities
Real-Time OS
Simulated Features
NOTE
Simulation for this device is provided by the default peripheral simulation driver.

Complete peripheral simulation is not available and is not planned to be implemented by ARM.

The following on-chip peripherals are simulated by the Keil Software µVision Debugger.

The following on-chip peripherals are not simulated.

  • Flash Memory
  • I²C Interface
  • Memory Accelerator Module
  • Memory Mapping Control

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