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Product Information Device Database® Downloads Compliance Testing Distributors | Digital Core Design DR8051CPUThe Digital Core Design DR8051CPU is an 8051 based Pipelined High Performance Microcontroller IP Core with DoCD - DCD on-Chip Debugger. It is available for FPGA and ASIC usages as fully synchronous design with single clock domain. Its architecture is 7 times faster compared to legacy 80C51, area optimized, and low power. Main features and peripherals: up to 64 KB on-chip/off-chip CODE 256 Bytes on-chip RAM, 16 MB XDATA, PMU - Power Management Unit, CODE/XDATA Wait State feature, 2 Interrupts/2 priority levels,.
Development Tools
Compiler, Assembler, Linker, Debugger |
Data Sheets 
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| Simulated Features The following on-chip peripherals are simulated by the Keil Software µVision Debugger. - 4 Clocks per Machine Cycle
- Clock Divider and Multiplier
- External Memory Stretch Cycle support
- Interrupts xS/2L (including external)
- Port 0
- Port 1
- Port 2
- Port 3
- Power save modes (Idle & Power down)
- Ring Oscillator
- Timer 0
- Timer 1
- Timer Rate Control
- Ultra High Speed (10 times faster)
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AGSI Drivers The following AGSI Drivers are available for the Keil Software µVision Simulator. |
AGDI Drivers The following AGDI Drivers are available for the Keil Software µVision Debugger. |
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