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Evaluation Software

Compliance Testing

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Digital Core Design DP8051XP

The Digital Core Design DP8051XP is an 8051 based Pipelined High Performance Microcontroller IP Core with DoCD - DCD on-Chip Debugger. It is available for FPGA and ASIC usages as fully synchronous design with single clock domain. Its architecture is 10 times faster compared to legacy 80C51. Main features and peripherals: up to 64 KB on-chip CODE, up to 64 KB off-chip CODE, 256 Bytes on-chip RAM, 16 MB XDATA, 2 DPTRs, CODE/XDATA Wait State feature, PMU - Power Management Unit, 15 Interrupts/2 priority levels, 32 I/O lines, 3 Timers/Counters, Watchdog timer, 2 UARTs, SPI - Serial Peripheral Interface, Master & Slave I2C, MDU - 16/32-bit Math Coprocessor, Floating Point Coprocessor,.

[Chip Vendor]

Evaluation Software
Data Sheets
Data Sheet for the Digital Core Design DP8051XP
Data Sheet
151,792 bytes
Instructions Set Details for the Digital Core Design DP8051XP
Instructions Set Details
261,432 bytes

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Header Files
Emulators
FLASH Utilities
Development Tools
Compiler, Assembler, Linker, Debugger
Simulated Features
NOTE
Simulation for this device is provided by the default peripheral simulation driver.

Complete peripheral simulation is not available at this time.
Real-Time OS
AGSI Drivers

The following AGSI Drivers are available for the Keil Software µVision Simulator.

AGDI Drivers

The following AGDI Drivers are available for the Keil Software µVision Debugger.

Consultants

The following consultants have experience with this device.