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µVision User's Guide

About µVision User Interface Creating Applications Debugging Start Debugging Start Energy Measurement without Debug Application Program Execution Debug Windows and Dialogs Breakpoints Window Call Stack and Locals Window Code Coverage Command Window Component Viewer Disassembly Window Editor Window Event Recorder Setup Event Recorder Event Recorder Window Events Filtering Event Statistics Window Post-mortem Analysis Event Viewer Execution Profiler Instruction Trace Window System Analyzer Usage tips Save System Analyzer Contents Statistics Restrictions Logic Analyzer Setup Setup in Detail Restrictions Cortex-M Trace Configuration Memory Map Memory Window Performance Analyzer Registers Window Serial Window Debug (printf) Viewer Symbols Window System Viewer Adding System Viewer Windows System and Thread Viewer Thread States Toolbox Trace Data Window Trace Navigation Trace Exceptions Event Counters ULINKplus Window Watch Window Core Peripherals Cortex-M0 and Cortex-M0+ Nested Vector Interrupt Controller System Control and Configuration System Tick Timer Fault Reports (Cortex-M0+ only) Cortex-M3, Cortex-M4, and Cortex-M7 Nested Vector Interrupt Controller System Control and Configuration System Tick Timer Fault Reports Memory Protection Unit Cortex-M23/M33/M35P and Cortex-M55 Nested Vector Interrupt Controller System Control and Configuration System Tick Timer Fault Reports Memory Protection Unit Security Attribution Unit M-Profile Vector Extension (MVE) Debug Scripting Expressions Constants System Variables Peripheral Variables I/O Ports Serial Ports Program Variables (Symbols) Fully Qualified Symbols Non-Qualified Symbols Literal Symbols Using Symbols Line Numbers Bit Addresses Type Specifications Memory Attribution Specifiers Operators Differences between µVision and C Expression Examples Code and Data Trace (Cortex-M) Trace Features Configuring Trace Tracepoint Expressions Tracepoint Intrinsics Tracepoint Limitations Tracepoint Marks Tips and Tricks Review Peripherals and CPU Configuration Simulate I/O Ports Simulate Interrupts and Clock Inputs Simulate external I/O Devices Assign Serial I/O to a PC COM Port Check Illegal Memory Access Command Input from File Preset I/O Ports or Memory Contents Write Debug Output to a File Keyboard Shortcuts TPIU Initialization after RESET (Cortex-M) Prevent Opening Files Show Japanese Messages Debug Commands Debug Functions Simulation Flash Programming Dialogs Utilities Command Line Example Programs Appendix


When debugging on hardware, the number of items that can be defined in the Logic Analyzer is restricted by the microcontroller core (refer to Access Breakpoints in ULINK Debug Adapters). Many more different items can be defined in simulation mode.

The Logic Analyzer can record changes of:

  • Up to four global program variables, including struct members (requires SWO trace).
  • VTREGs that represent I/O pins of the microcontroller (only in simulation).
  • Peripheral registers that are triggered by external or internal events, but with the restrictions outlined below (only in simulation).

The Logic Analyzer cannot record changes of:

  • Automatic variables defined inside a function
    Automatic variables are located on the stack or in overlayable memory regions. It is not possible to record changes of dynamic memory locations.
  • CPU registers
    CPU registers cannot be triggered with read or write breakpoints. Therefore, such changes cannot be recorded.
  • Peripheral registers that represent timer registers
    Increments of timers (or similar peripherals) are not simulated. Instead, the timing of events that are triggered by a timer, is calculated. Therefore, it is not possible to view timer increments.
  • I/O pins of communication peripherals
    I/O pin toggling of UART, CAN, SPI, or I²C communication peripherals is not simulated. It is assumed that the timing of communication streams behaves according to the specifications. Instead, the I/O stream is represented by VTREGs.
  • Memory BUS signals
    µVision simulates a CPU including memory areas, but it does not simulate the Memory BUS signals (data BUS, address BUS, and control lines like RD, WR, ALE). Therefore, it is not possible to view memory BUS signals with the Logic Analyzer.
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