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µVision User's Guide

About µVision User Interface Creating Applications Debugging Start Debugging Start Energy Measurement without Debug Application Program Execution Debug Windows and Dialogs Breakpoints Window Call Stack and Locals Window Code Coverage Command Window Component Viewer Disassembly Window Editor Window Event Recorder Setup Event Recorder Event Recorder Window Events Filtering Event Statistics Window Post-mortem Analysis Event Viewer Execution Profiler Instruction Trace Window System Analyzer Usage tips Save System Analyzer Contents Statistics Restrictions Logic Analyzer Setup Setup in Detail Restrictions Cortex-M Trace Configuration Memory Map Memory Window Performance Analyzer Registers Window Serial Window Debug (printf) Viewer Symbols Window System Viewer Adding System Viewer Windows System and Thread Viewer Thread States Toolbox Trace Data Window Trace Navigation Trace Exceptions Event Counters ULINKplus Window Watch Window Core Peripherals Cortex-M0 and Cortex-M0+ CM0/M0+: Nested Vector Interrupt Controller CM0/M0+: System Control and Configuration CM0/M0+: System Tick Timer Fault Reports (Cortex-M0+ only) Cortex-M3, Cortex-M4, and Cortex-M7 CM3/M4/M7: Nested Vector Interrupt Controller CM3/M4/M7: System Control and Configuration CM3/M4/M7: System Tick Timer CM3/M4/M7: Fault Reports CM3/M4/M7: Memory Protection Unit Cortex-M23/M33/M35P and Cortex-M55 Armv8-M: Nested Vector Interrupt Controller Armv8-M: System Control and Configuration Armv8-M: System Tick Timer Armv8-M: Fault Reports Armv8-M: Memory Protection Unit Armv8-M: Security Attribution Unit M-Profile Vector Extension (MVE) Debug Scripting Expressions Constants System Variables Peripheral Variables I/O Ports Serial Ports Program Variables (Symbols) Fully Qualified Symbols Non-Qualified Symbols Literal Symbols Using Symbols Line Numbers Bit Addresses Type Specifications Memory Attribution Specifiers Operators Differences between µVision and C Expression Examples Code and Data Trace (Cortex-M) Trace Features Configuring Trace Tracepoint Expressions Tracepoint Intrinsics Tracepoint Limitations Tracepoint Marks Tips and Tricks Review Peripherals and CPU Configuration Simulate I/O Ports Simulate Interrupts and Clock Inputs Simulate external I/O Devices Assign Serial I/O to a PC COM Port Check Illegal Memory Access Command Input from File Preset I/O Ports or Memory Contents Write Debug Output to a File Keyboard Shortcuts TPIU Initialization after RESET (Cortex-M) Prevent Opening Files Show Japanese Messages Debug Commands Debug Functions Simulation Flash Programming Dialogs Utilities Command Line Example Programs Appendix

CM3/M4/M7: System Control and Configuration

The System Control and Configuration dialog (for Cortex-M3, Cortex-M4, and Cortex-M7) shows controls about low power state and some aspects of the processor behavior.

picture: M347_SCC

You can configure (where applicable) the processor behavior using the following control groups:

System Control
The System Control Register (SCR) controls features of entry to and exit from low power state and is located at memory address 0xE000ED10.


SCB->SCR Content of the SCR in Hex. Reset value is 0x00000000.
SLEEPONEXIT Determines whether, on exit from an ISR that returns to the base level of execution, the processor enters a sleep state.
SLEEPDEEP Controls whether the processor uses sleep or deep sleep as its low power mode:
  • 0 (unchecked) = sleep.
  • 1 (checked) = deep sleep.
If your device does not support two sleep modes, then the effect of changing the value of this bit is implementation-defined.
SEVONPEND Send Event on Pending bit:
  • 0 (unchecked) = only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded.
  • 1 (checked) = enabled events and all interrupts, including disabled interrupts, can wakeup the processor.
When an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, then the event is registered and affects the next WFE. The processor also wakes up on execution of an SEV instruction or an external event.
Configuration Control
Shows the Configuration and Control Register (CCR) settings. The CCR is a read-only register.


SCB->CCR Shows the content of the CCR register (in HEX) located at memory address 0xE000ED14. The reset value is 0x00000200, however, it is implementation-defined.
NONBASETHRDENA Indicate how the processor enters Thread mode:
  • 0 (unchecked) - Processor can enter Thread mode only when no exception is active.
  • 1 (checked) - Processor can enter Thread mode from any level under the control of an EXC_RETURN value. Exception return (EXC_RETURN) occurs when the processor is in Handler mode and executes one of the following instructions attempts to set the PC to an EXC_RETURN value:
    • an LDM or POP instruction that loads the PC.
    • an LDR instruction with PC as the destination.
    • a BX instruction using any register.
USERSETMPEND Enable (when checked) unprivileged software access to the Software Trigger Interrupt Register (STIR). Refer also to NVIC, section Software Interrupt Trigger.
UNALIGN_TRP Enable unaligned access traps:
  • 0 (unchecked) - Do not trap unaligned halfword and word accesses.
  • 1 (checked) - Trap unaligned halfword and word accesses. An unaligned access generates a UsageFault. Unaligned LDM, STM, LDRD, and STRD instructions.
DIV_0_TRP Enable faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0:
  • 0 (unchecked) - Do not trap divide by 0; a divide by zero returns a quotient of 0.
  • 1 (checked) - Trap divide by 0.
BFHFNMIGN Enable handlers with priority -1 or -2 to ignore data BusFaults caused by load and store instructions. This applies to the HardFault, NMI, and FAULTMASK escalated handlers:
  • 0 (unchecked) - data bus faults caused by load and store instructions cause a lock-up.
  • 1 (checked) - handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions. Set this bit to 1 only when the handler and its data are in absolutely safe memory. The normal use of this bit is to probe system devices and bridges to detect control path problems and fix them.
STKALIGN Indicates stack alignment on exception entry:
  • 0 (unchecked) - 4-byte aligned.
  • 1 (checked) - 8-byte aligned.
On exception entry, the processor uses bit[9] of the stacked PSR to indicate the stack alignment. On return from the exception it uses this stacked bit to restore the correct stack alignment.
(Cortex-M7 only)
Enable L1 data cache. This bit is optional:
  • 0 (unchecked) - L1 data cache disabled.
  • 1 (checked) - L1 data cache enabled.
(Cortex-M7 only)
Enables L1 instruction cache. This bit is optional:
  • 0 (unchecked) - L1 instruction cache disabled.
  • 1 (checked) - L1 instruction cache enabled.
(Cortex-M7 only)
It indicates branch prediction is enabled. Always reads-as-one.

Application access to the SCR and CCR

You can access peripheral registers and related functions from the user application. As a minimum, the files <device>.h and <core_cm#>.h define the register layout, base addresses, and access definitions. Refer to CMSIS-CORE – Peripheral Access for details.

Refer to Intrinsic Functions for CPU Instructions for the set of available functions in CMSIS, specifically __WFE and __SEV.

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