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µVision User's Guide

About µVision User Interface Creating Applications Debugging Start Debugging Start Energy Measurement without Debug Application Program Execution Debug Windows and Dialogs Breakpoints Window Call Stack and Locals Window Code Coverage Command Window Component Viewer Disassembly Window Editor Window Event Recorder Setup Event Recorder Event Recorder Window Events Filtering Event Statistics Window Post-mortem Analysis Event Viewer Execution Profiler Instruction Trace Window System Analyzer Usage tips Save System Analyzer Contents Statistics Restrictions Logic Analyzer Setup Setup in Detail Restrictions Cortex-M Trace Configuration Memory Map Memory Window Performance Analyzer Registers Window Serial Window Debug (printf) Viewer Symbols Window System Viewer Adding System Viewer Windows System and Thread Viewer Thread States Toolbox Trace Data Window Trace Navigation Trace Exceptions Event Counters ULINKplus Window Watch Window Core Peripherals Cortex-M0 and Cortex-M0+ CM0/M0+: Nested Vector Interrupt Controller CM0/M0+: System Control and Configuration CM0/M0+: System Tick Timer Fault Reports (Cortex-M0+ only) Cortex-M3, Cortex-M4, and Cortex-M7 CM3/M4/M7: Nested Vector Interrupt Controller CM3/M4/M7: System Control and Configuration CM3/M4/M7: System Tick Timer CM3/M4/M7: Fault Reports CM3/M4/M7: Memory Protection Unit Cortex-M23/M33/M35P and Cortex-M55 Armv8-M: Nested Vector Interrupt Controller Armv8-M: System Control and Configuration Armv8-M: System Tick Timer Armv8-M: Fault Reports Armv8-M: Memory Protection Unit Armv8-M: Security Attribution Unit M-Profile Vector Extension (MVE) Debug Scripting Expressions Constants System Variables Peripheral Variables I/O Ports Serial Ports Program Variables (Symbols) Fully Qualified Symbols Non-Qualified Symbols Literal Symbols Using Symbols Line Numbers Bit Addresses Type Specifications Memory Attribution Specifiers Operators Differences between µVision and C Expression Examples Code and Data Trace (Cortex-M) Trace Features Configuring Trace Tracepoint Expressions Tracepoint Intrinsics Tracepoint Limitations Tracepoint Marks Tips and Tricks Review Peripherals and CPU Configuration Simulate I/O Ports Simulate Interrupts and Clock Inputs Simulate external I/O Devices Assign Serial I/O to a PC COM Port Check Illegal Memory Access Command Input from File Preset I/O Ports or Memory Contents Write Debug Output to a File Keyboard Shortcuts TPIU Initialization after RESET (Cortex-M) Prevent Opening Files Show Japanese Messages Debug Commands Debug Functions Simulation Flash Programming Dialogs Utilities Command Line Example Programs Appendix

CM0/M0+: Nested Vector Interrupt Controller

The Nested Vectored Interrupt Controller dialog (for Cortex-M0 and Cortex-M0+) shows the status of all exceptions. For each exception, the dialog shows the number, source, name, state, and priority.


You can select and configure (where applicable) each exception using the following control groups:

Selected Interrupt
This group shows exception-specific controls.


Enable Enable (NVIC->ISER) or disable (NVIC->ICER) the selected exception. For some exceptions, this is read-only. When unchecked, the exception cannot be taken. This control corresponds to the column E in the list.
Pending You can manually trigger an exception by setting this (NVIC->ISPR) For some exceptions, this is write-1-only. Note that an exception can get into the state pending, though it is disabled. This control corresponds to the column P in the list.
Priority Shows the priority of the selected exception. Can be set manually for user-defined exceptions. This control corresponds to the column Priority in the list. For system exceptions, the register NVIC->IP is written, while for user defined exceptions the register SCB->SHP is written.
Each exception is in one of the following states:
  • Inactive - The exception is not active and not pending.
  • Pending - The exception is waiting to be serviced by the processor. An interrupt request from a peripheral or from software can change the state of the corresponding interrupt to pending.
  • Active - An exception that is being serviced by the processor but has not completed. An exception handler can interrupt the execution of another exception handler. In this case, both exceptions are in the active state.
  • Active and pending - The exception is being serviced by the processor and there is a pending exception from the same source.
Interrupt Control & State
The Interrupt Control and State Register (ICSR) at memory address 0xE000ED04:
  • Provides a set-pending bit for the Non-Maskable Interrupt (NMI) exception.
  • Provides set-pending and clear-pending bits for the PENDSV and SYSYTICK exceptions.
  • Shows the exception number of the highest priority pending exception.


INT_CTRL_ST Content of the ICSR in Hex.
ISRPENDING Exception pending flag. Shows that at least one exception is pending, excluding NMI and faults.
ISRPREEMPT The next pending exception becomes active.
VECTACTIVE Number of the active exception.
VECTPENDING Shows the number of the enabled exception with the highest priority that is pending, including NMI and faults.
Application Interrupt & Reset Control
The AIRCR at memory address 0xE000ED0C provides endian status for data accesses and reset control of the system.


AIRC Content of AIRCR in Hex. Default value is 0xFA050000.
ENDIANNESS Shows the significant byte order of a word. Is read-only. When unchecked = little-endian; when checked = big-endian.
SYSRESETREQ Click to raise the external signal for reset. Always reads as zero.
VECTCLRACTIVE Click to clear state information.
Vector Table Offset
Only available for Cortex-M0+. Is an optional register located at memory address 0xE000ED08.


VTO Contains the vector table settings. Default value is 0x00000000.
TBLOFF Shows the vector table offset from Code or RAM.
TBLBASE Indicates if the table is in Code or RAM.

Application access to the NVIC registers

You can access peripheral registers and related functions from the user application. As a minimum, the files <device>.h and <core_cm#>.h define the register layout, base addresses, and access definitions. Refer to CMSIS-CORE – Peripheral Access for details.

Refer to Interrupts and Exceptions (NVIC) for the set of available NVIC functions in CMSIS.

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