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µVision User's Guide

About µVision User Interface Creating Applications Debugging Start Debugging Start Energy Measurement without Debug Application Program Execution Debug Windows and Dialogs Breakpoints Window Call Stack and Locals Window Code Coverage Command Window Component Viewer Disassembly Window Editor Window Event Recorder Setup Event Recorder Event Recorder Window Events Filtering Event Statistics Window Post-mortem Analysis Event Viewer Execution Profiler Instruction Trace Window System Analyzer Usage tips Save System Analyzer Contents Statistics Restrictions Logic Analyzer Setup Setup in Detail Restrictions Cortex-M Trace Configuration Memory Map Memory Window Performance Analyzer Registers Window Serial Window Debug (printf) Viewer Symbols Window System Viewer Adding System Viewer Windows System and Thread Viewer Thread States Toolbox Trace Data Window Trace Navigation Trace Exceptions Event Counters ULINKplus Window Watch Window Core Peripherals Cortex-M0 and Cortex-M0+ CM0/M0+: Nested Vector Interrupt Controller CM0/M0+: System Control and Configuration CM0/M0+: System Tick Timer Fault Reports (Cortex-M0+ only) Cortex-M3, Cortex-M4, and Cortex-M7 CM3/M4/M7: Nested Vector Interrupt Controller CM3/M4/M7: System Control and Configuration CM3/M4/M7: System Tick Timer CM3/M4/M7: Fault Reports CM3/M4/M7: Memory Protection Unit Cortex-M23/M33/M35P and Cortex-M55 Armv8-M: Nested Vector Interrupt Controller Armv8-M: System Control and Configuration Armv8-M: System Tick Timer Armv8-M: Fault Reports Armv8-M: Memory Protection Unit Armv8-M: Security Attribution Unit M-Profile Vector Extension (MVE) Debug Scripting Expressions Constants System Variables Peripheral Variables I/O Ports Serial Ports Program Variables (Symbols) Fully Qualified Symbols Non-Qualified Symbols Literal Symbols Using Symbols Line Numbers Bit Addresses Type Specifications Memory Attribution Specifiers Operators Differences between µVision and C Expression Examples Code and Data Trace (Cortex-M) Trace Features Configuring Trace Tracepoint Expressions Tracepoint Intrinsics Tracepoint Limitations Tracepoint Marks Tips and Tricks Review Peripherals and CPU Configuration Simulate I/O Ports Simulate Interrupts and Clock Inputs Simulate external I/O Devices Assign Serial I/O to a PC COM Port Check Illegal Memory Access Command Input from File Preset I/O Ports or Memory Contents Write Debug Output to a File Keyboard Shortcuts TPIU Initialization after RESET (Cortex-M) Prevent Opening Files Show Japanese Messages Debug Commands Debug Functions Simulation Flash Programming Dialogs Utilities Command Line Example Programs Appendix

Armv8-M: Nested Vector Interrupt Controller

The Nested Vectored Interrupt Controller (NVIC) dialog (for ARMv8 architecture) shows the status of all exceptions, including exceptions that have Secure (S) and Non-secure (NS) states. For example, SYSTICK (S) and SYSTICK (NS). For each exception, the dialog shows the number, source, name, state, and priority.

picture: ARMv8_NVIC

You can select and configure (where applicable) each exception using the following control groups:

Selected Interrupt
Show and change values for a selected interrupt or exception source.


Enable Is the interrupt enable control. This control corresponds to the column E in the list.
Pending Indicates that an interrupt is waiting to be serviced (for some exceptions, this is write-1-only). This control corresponds to the column P in the list.
Active Indicates that this interrupt is being serviced. This control corresponds to the column A in the list.
Secure Indicates the secure state of an exception. This control corresponds to the column TZ in the list.
Priority Is the interrupt priority in the format: <priority value> = <group priority> s<subpriority>. The group priority determines preemption of interrupts. This control corresponds to the column Priority in the list.
The displayed register is NVIC->IPR (for exceptions) or SCB->SHPR (for interrupts).
Each exception is in one of the following states:
  • Inactive - The exception is not active and not pending.
  • Pending - The exception is waiting to be serviced by the processor. An interrupt request from a peripheral or from software can change the state of the corresponding interrupt to pending.
  • Active - An exception that is being serviced by the processor but has not completed. An exception handler can interrupt the execution of another exception handler. In this case, both exceptions are in the active state.
  • Active and pending - The exception is being serviced by the processor and there is a pending exception from the same source.
Interrupt Control & State
The Interrupt Control and State Register (ICSR) at memory address 0xE000ED04:
  • Provides a set-pending bit for the Non-Maskable Interrupt (NMI) exception.
  • Provides set-pending and clear-pending bits for the PENDSV and SYSYTICK exceptions.
  • Shows the exception number of the highest priority pending exception.


SCB->ICSR Content of the ICSR in Hex.
RETTOBASE Indicates whether there are preempted active exceptions:
  • 0 (unchecked) - there are preempted active exceptions to execute
  • 1 (checked) - there are no active exceptions, or the currently executing exception is the only active exception.
ISRPREEMPT The next pending exception becomes active.
VECTACTIVE Number of the active exception. The number 0 indicates thread mode.
VECTPENDING Shows the number of the enabled exception with the highest priority that is pending, including NMI and faults.
ISRPENDING Exception pending flag. Shows that at least one exception is pending, excluding NMI and faults.
STNS Shows the value for SysTick Targets Non-secure (STTNS). Controls whether in a single SysTick implementation, the SysTick is Secure or Non-secure. This bit is not banked between Security states.
  • 0 (unchecked) - SysTick is Secure.
  • 1 (checked) - SysTick is Non-secure.
Application Interrupt & Reset Control
The AIRCR at memory address 0xE000ED0C provides endian status for data accesses and reset control for the Secure state.
The AIRCR (NS) at memory address 0xE002ED0C provides endian status for data accesses and reset control for the Non-secure state.


AIRCR Content of AIRCR in Hex. Default value is 0xFA050000 for the Non-secure state, and 0xFA054000 for the Secure state.
PRIGROUP The interrupt priority grouping field is implementation defined. This field determines the split of group priority from subpriority. This field is banked between Security states. If the Main Extension is not implemented, then this field is RES0.
ENDIANNESS Shows the significant byte order of a word. This bit is not banked between Security states.
  • 0 (unchecked) - Little-endian.
  • 1 (checked) - Big-endian.
BFHFNMINS BusFault, HardFault, and NMI Non-secure enable. The value of this bit defines whether BusFault and NMI exceptions are Non-secure, and whether exceptions target the Non-secure HardFault exception. This bit is not banked between Security states. This bit is read-only from Non-secure. The possible values of this bit are:
  • 0 (unchecked) - BusFault, HardFault, and NMI are Secure.
  • 1 (checked) - BusFault and NMI are Non-secure and exceptions can target Non-secure HardFault.
PRIS Defines whether Secure exception priority boosting is enabled:
  • 0 (unchecked) - Priority ranges of Secure and Non-secure exceptions are identical.
  • 1 (checked) - Non-secure exceptions are de-prioritized.
SYSRESETREQS System reset request Secure only. The value of this bit defines whether the SYSRESETREQ bit is functional for Non-secure use. This bit is not banked between Security states.
  • 0 (unchecked) - SYSRESETREQ functionality is available to both Security states.
  • 1 (checked) - SYSRESETREQ functionality is only available to Secure state.
VECTRESETREQ System reset request. This bit allows software or a debugger to request a system reset. This bit is not banked between Security states. Click to request a system reset.
VECTCLRACTIVE Click to clear active state information in the following way:
  • IPSR is cleared to zero.
  • The active state for all Non-secure exceptions is cleared.
  • If DHCSR.S_SDE==1, the active state for all Secure exceptions are cleared.
This bit is not banked between Security states.
Vector Table Offset
Is an optional register located at memory address 0xE000ED08 for Non-secure and 0xE002ED08 secure state.


SCB->VTOR Contains the vector table settings. Default value is 0x00000000.
TBLOFF Shows the vector table offset from Code or RAM.
TBLBASE Indicates if the table is in Code or RAM.
Software Interrupt Trigger
The Software Trigger Interrupt Register (STIR) is located at memory address 0xE000EF00.
When the USERSETMPEND bit in the System Control and Configuration is set to 1, unprivileged software can access the STIR.


SCB->STIR Contains the STIR value in HEX. Write to the STIR to generate an interrupt from software. Default value is 0x00000000.
INTID Interrupt ID of the interrupt to trigger, in the range [0-239]. For example, a value of 0x03 specifies interrupt IRQ3.

Application access to the NVIC registers

You can access peripheral registers and related functions from the user application. As a minimum, the files <device>.h and <core_cm#>.h define the register layout, base addresses, and access definitions. Refer to CMSIS-CORE � Peripheral Access for details.

Refer to Interrupts and Exceptions (NVIC) for the set of available NVIC functions in CMSIS.

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