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µVision User's Guide

About µVision User Interface Creating Applications Debugging Start Debugging Start Energy Measurement without Debug Application Program Execution Debug Windows and Dialogs Breakpoints Window Call Stack and Locals Window Code Coverage Command Window Component Viewer Disassembly Window Editor Window Event Recorder Setup Event Recorder Event Recorder Window Events Filtering Event Statistics Window Post-mortem Analysis Event Viewer Execution Profiler Instruction Trace Window System Analyzer Usage tips Save System Analyzer Contents Statistics Restrictions Logic Analyzer Setup Setup in Detail Restrictions Cortex-M Trace Configuration Memory Map Memory Window Performance Analyzer Registers Window Serial Window Debug (printf) Viewer Symbols Window System Viewer Adding System Viewer Windows System and Thread Viewer Thread States Toolbox Trace Data Window Trace Navigation Trace Exceptions Event Counters ULINKplus Window Watch Window Core Peripherals Cortex-M0 and Cortex-M0+ Nested Vector Interrupt Controller System Control and Configuration System Tick Timer Fault Reports (Cortex-M0+ only) Cortex-M3, Cortex-M4, and Cortex-M7 Nested Vector Interrupt Controller System Control and Configuration System Tick Timer Fault Reports Memory Protection Unit Cortex-M23/M33/M35P and Cortex-M55 Nested Vector Interrupt Controller System Control and Configuration System Tick Timer Fault Reports Memory Protection Unit Security Attribution Unit M-Profile Vector Extension (MVE) Debug Scripting Expressions Constants System Variables Peripheral Variables I/O Ports Serial Ports Program Variables (Symbols) Fully Qualified Symbols Non-Qualified Symbols Literal Symbols Using Symbols Line Numbers Bit Addresses Type Specifications Memory Attribution Specifiers Operators Differences between µVision and C Expression Examples Code and Data Trace (Cortex-M) Trace Features Configuring Trace Tracepoint Expressions Tracepoint Intrinsics Tracepoint Limitations Tracepoint Marks Tips and Tricks Review Peripherals and CPU Configuration Simulate I/O Ports Simulate Interrupts and Clock Inputs Simulate external I/O Devices Assign Serial I/O to a PC COM Port Check Illegal Memory Access Command Input from File Preset I/O Ports or Memory Contents Write Debug Output to a File Keyboard Shortcuts TPIU Initialization after RESET (Cortex-M) Prevent Opening Files Show Japanese Messages Debug Commands Debug Functions Simulation Flash Programming Dialogs Utilities Command Line Example Programs Appendix

Memory Protection Unit

The Memory Protection Unit (MPU) dialog shows the MPU Control Register and the memory map of the MPU, the number of regions with the location, size, access permissions, and memory attributes of each region. The following applies to an MPU:

  • the default memory map can be configured to provide a background region for privileged accesses.
  • the MPU divides the memory into regions. The number of supported regions is IMPLEMENTATION DEFINED.
  • All regions are aligned to a multiple of 32 bytes.
  • The MPU is restricted in how it can change the default memory map attributes associated with System space.

For a correct configuration of your MPU, refer to the Device Generic User Guide that corresponds to the core of your device.

picture: ARMv8_MPU

You can select and configure (where applicable) each memory region using the following control groups:

Enable or disable the MPU.
  • 0 (unchecked) - MPU is disabled. Privileged and unprivileged accesses use the default memory map. If no MPU regions are implemented, this bit is RES0.
  • 1 (checked) - MPU is enabled.
List of Memory Regions
Shows the list of memory regions, Secure and Non-secure, with all attributes.


EN Enable or disable the selected memory region.
  • 0 (unchecked) - Region disabled.
  • 1 (checked) - Region enabled.
Start Address Is the region base address field, represented by ADDR from the Region Base Address Register (MPU_RBAR).
End Address Specify the upper limit of the memory region.
XN Execute never bit. Defines whether code can be executed from this region.
  • 0 (unchecked) - Execution only permitted if read permitted.
  • 1 (checked) - Execution not permitted.
AP Access permission field. The possible values of this field are listed in the drop down.
SH Shareability. Defines the Shareability domain of this region for Normal memory. The possible values of this field are listed in the drop down. For any type of Device memory, the value of this field is ignored.
Attr Attribute index number. This number corresponds to the number listed in section Attr 0..7. Assign the attribute number to associate the settings with a region.
Attributes Corresponds to the Outer and Inner settings of section Attr 0..7 and the MPU_MAIR1 or MPU_MAIR0 registers.
S Shareable bit. Select the setting from the drop-down.
Represents the MPU Control Register (MPU_CTRL) located at memory address 0xE000ED94 for Secure and 0xE002ED94 Non-secure state. The single bit assignments are listed below.


field Represents the MPU Control Register (MPU_CTRL) The single bit assignments are listed below.
HFNMIENA Enable the operation of MPU during HardFault, NMI, and FAULTMASK handlers. When the MPU is enabled:
  • 0 (unchecked) - MPU is disabled during HardFault, NMI, and FAULTMASK handlers, regardless of the value of the ENABLE bit.
  • 1 (checked) - The MPU is enabled during HardFault, NMI, and FAULTMASK handlers. When the MPU is disabled and this bit is set, then the behavior is unpredictable.
PRIVDEFENA Enable privileged software access to the default memory map when the MPU is enabled. If the MPU is disabled, then the processor ignores this bit.
  • 0 (unchecked) - Disable the use of the default memory map. Any access to a memory location not covered by an enabled region causes a fault.
  • 1 (checked) - Enable the use of the default memory map as a background region for privileged software accesses.
MPU Attribute Indirection Regsiter 0 / 1
Represents the settings of Memory Attribute Indirection Register 0 (MPU_MAIR0) and Register 1 (MPU_MAIR1).
MPU_MAIR0 register located at 0xE000EDC0 (Secure) and 0xE002EDC0 (Non-secure) memory address.
MPU_MAIR1 register located at 0xE000EDC4 (Secure) and 0xE002EDC4 (Non-secure) memory address.
Provides the memory attribute encoding that correspond to the AttrIndex values.


Attr(m) Memory attribute encoding for MPU regions with an AttrIndex of m.
Attr 0..7
Defines the memory attribute encoding for use in the MPU_MAIR0 and MPU_MAIR1. Values can be assigned from the drop-downs.


# Is the attribute index.
Outer Outer attributes. Specify the Outer memory attributes.
Inner Device attributes.
  • When Outer=='0000' - specify the memory attributes for Device.
  • When Outer!='0000' - specify the Inner memory attributes.
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