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CoreSight Technology

CoreSight™ is an on-chip debugging and tracing technology designed by ARM. The device manufacturer can implement CoreSight features in various combinations. For a list of advantages refer to Streaming Trace.

CoreSight Features

CoreSight features can be accessed through a JTAG or Serial Wire interface. Debugging in JTAG and Serial Wire mode at the same time is not possible. Cortex-M processor-based devices can include a:

Debug Interface

The supported debug modes are:

  • JTAG Debug is the industry-standard interface that allows device chaining.
  • Serial Wire Debug is a 2-pin interface with an optional Serial Wire Trace Output. Contrary to JTAG, devices cannot be chained.

The Serial Wire-JTAG Switch (SWJ) synchronizes the debugger adapter and the CoreSight debug interface. ULINKpro uses this option to generate sequences for switching between Serial Wire Debug and JTAG Debug mode.

The Debug Interface communicates with the following units:

  • Run Control: allows the user to start, stop, and single-step through the source code.
  • Breakpoint Unit: allows the user to set breakpoints even while the processor is running.
  • Memory Access Unit: allows the user to read or write to memory and peripheral registers even while the program is running.

Trace Interface

The Trace Interface encodes and provides trace information via:

  • The Serial Wire Trace Output (SWO) pin, which can be used only in combination with the Serial Wire Debug mode. SWO does not support ETM trace data.
  • The 4-Pin Trace Output, which has a greater bandwidth than the Serial Wire Trace Output and uses 5 functional pins.
  • The Embedded Trace Buffer (ETB), which provides on-chip storage of trace data using 32-bit RAM. Data is accessed through registers. No additional output-pins are needed.

The Trace Interface communicates with the following units:

  • Embedded Trace Macrocell (ETM): provides instruction tracing to debug historical sequences, for software profiling and code coverage analysis. ETM data are output through an extra 4-bit interface.
  • Instrumentation Trace Macrocell (ITM): provides application information like debug printf(), RTOS information, unit test, or UML annotation.
  • Data Watchpoint & Trace Unit (DWT): provides PC sampling, event counters, timing, and interrupt execution information. In addition, it allows Access Breakpoints for up to four memory addresses.


The two standard connectors are recommended:

  • 10-pin Cortex Debug for JTAG or Serial Wire Debug and Trace.
  • 20-pin Cortex Debug+ETM connector adds to the Cortex Debug connector ETM trace pins.


  • The manufacturer's device data sheet describes the implemented CoreSight features.
  • The chapter Debug Driver describes the ULINKpro configuration options for the Debug Interface.
  • The chapter Trace Configuration describes the ULINKpro configuration options for the Trace Interface.
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