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Cortex-M0+/M23 MTB Devices

Many Cortex-M0+ and Cortex-M23-based devices provide simple instruction trace support by integrating Arm© CoreSightTM Micro Trace Buffer (MTB) technology.

When MTB is enabled, the trace data is stored in a user-configurable circular on-chip trace buffer that is located in device RAM and shares it with the executed application. It is crucial to ensure that MTB area in RAM is not used for the application variables, stack, and heap. Once the program is stopped, the debugger transfers the trace frames currently in the RAM to the Trace Instruction window on the host computer.

The device, the debugger adapter, and µVision have to be configured properly to capture MTB trace on such targets:


  • If an Microcontroller Prototyping System (MPS) is used, then the Cortex-M0 MTB IP image has to be programmed into this unit.
  • Application examples are located in the folder \ARM\Boards\ARM\MPS_CM0MTB. The examples are configured to be used with an MPS.
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