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Trace

The Trace dialog defines generation and capturing of trace events. ULINKplus delivers trace information in real-time to the host PC.

Target Driver Setup - Trace

Note

  • While the debugger is running the Status Bar indicates the trace capturing operation.

General settings define system clock frequency and overall trace capturing.

General Trace Settings

Core Clock
Specify the processor core clock frequency here. The debugger uses this value to calculate timings for trace capturing and displays (such as current and voltage for example), even when trace is disabled. It also configures the debug unit's trace capture UART device. It should be be set to the system clock frequency that your target application uses in active state. If in doubt, use the Clock Measurement capabilities of ULINKplus to verify the correct setting. If your device's trace clock does not run as fast as the system core clock, specify a separate Trace Clock.
Trace Clock
Specify the trace clock frequency here, if it differs from the Core Clock. It is available for editing when Use Core Clock is unchecked.
Trace Enable
Enable this option to capture trace events.
Use Core Clock
Enable this option to use the core clock frequency for trace. If your trace clock differs, uncheck and enter the correct trace clock in the Trace Clock box.
ETM Trace Enable
Instructs the debugger to capture Instruction Trace data from the device. It becomes available for configuration when Embedded Trace Buffer (ETB) is selected as the Trace Port. Along with enabling this checkbox, the ETB shall also be enabled on the device, for example using an Initialization File. See Common Options in µVision Debug dialog

Trace Port defines the port type and its parameters. Two options are supported in ULINKplus:

  • Serial Wire Output - UART/NRZ relies on the Serial Wire Trace Output pin (SWO) for obtaining trace data. Port must be set to SW (Serial Wire) in the Debug dialog.

    Trace Port Settings SWO

    SWO trace port has following configuration parameters:
    SWO Clock Prescaler
    Defines the prescaler setting for the SWO clock divider. Increase this to reduce Hardware Buffer Overrun errors. Decrease this to reduce Trace Data Overflow errors.
    Autodetect
    Enable this option to configure the highest possible SWO clock rate ULINKplus will run at. It will be calculated using the given Trace or Core Clock setting
    SWO Clock
    Displays the actual configured SWO clock rate.
  • Embedded Trace Buffer relies for tracing on the on-chip Embedded Trace Buffer (ETB). ETB uses on-chip memory for trace data storage. Data is accessed by the debugger through registers without using any additional pins. Refer to your device user manual for information about ETB support.
    When Embedded Trace Buffer is selected, the option ETM Trace Enable becomes active.

    Trace Port Settings ETB

    Note

    • µVision does not provide time information for ETB trace.
    • Code coverage is not supported for ETB trace.
    • You can read the ETB buffer while the CPU is running if a TraceHalt tracepoint was hit before.

Timestamps control timing information created within the trace stream.

Trace Timestamps

Enable
Activate timestamps that are appended to trace packets.
Prescaler
Granularity of the timestamps (Core Clock divided by the Prescaler); set to 1 for best accuracy.

Note

  • Enable timestamps for correct timing information (for example in the System Analyzer).
  • Increase the Prescaler value if trace capture errors are shown in the Status Bar .
  • PC Sampling timestamps are reconstructed for the given period and timestamps will be shown for them even if the Enable option is not selected.

PC Sampling controls generation of program counter (PC) values within the trace stream.

Trace PC Sampling

Prescaler
Frequency of periodic PC values (Core Clock divided by Prescaler).
Periodic
Enables PC values at regular intervals.
Period
Displays the timing of the PC sampling interval.
on Data R/W Sample
Generate PC values for memory read/write trace capturing. Enable this option to show the program location that caused the memory accesses.

Note

  • Disable Periodic PC sampling or increase the Prescaler value if trace capture errors are shown in the Status Bar .

Trace Events enable the trace capturing of exceptions, interrupts, and Event Counters.

Trace PC Sampling

CPI: Cycles per Instruction
Indicates additional wait states during program execution: this counter increments on each additional cycle required to execute instructions (for example stalls caused by the memory system).
EXC: Exception Overhead
This counter increments on each cycle associated with exception stack operations (entry, return, preemption) and other exception-related processes.
SLEEP: Sleep Cycles
This counter increments on each cycle associated with power saving, whether initiated by a WFI or WFE instruction, or by the sleep-on-exit functionality.
LSU: Load Store Unit Cycles
This counter increments on each additional cycle required to execute a multi-cycle load-store instruction.
FOLD: Folded Instructions
This counter increments on any instruction that executes in zero cycles (for example, an IT instruction is folded and does not use any cycles).
EXCTRC: Exception Tracing
Include information about exception and interrupt execution in the trace stream. The Trace Exceptions window shows statistics and System Analyzer displays exceptions over time.

Note

  • Disable some options if trace capture errors are shown in the Status Bar .

ITM Stimulus Ports control trace events generated with the Instrumentation Trace Macrocell (ITM).

Trace PC Sampling

Enable
Enable an ITM port with individual check-boxes or type a value into the field.
  • Enable Port 0 to view data in the serial window Debug (printf) Viewer.
  • Enable Port 31 to view RTX events in Kernel Awareness windows.
Privilege
Define access rights for a group of 8 ITM ports.
  • Enable an ITM port to protect access in thread mode (privilege mode can always access ITM ports).
  • Disable to allow access in any mode.
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