Keil Logo

C16xU and C165UTAH Devices

Due to hardware restrictions on the C161U, C165H, and C165UTAH, OCDS debugging is only fully supported when the application code resides in off-chip RAM.

Using the Infineon EASY UTAH Board

On the Infineon EASY UTAH board you need to set Jumper JP7 ON to use the LPT/OCDS interface (Wiggler). When Jumper JP7 is OFF the OCDS connector is enabled and you can connect the XC16Board to the Keil ULINK.

An example application that is configured for OCDS debugging with the Infineon EASY UTAH board is available in the folder: ..\C166\Examples\Boards\Infineon EASY UTAH.

Using an OCDS Connector

An OCDS connector can be easily added to user hardware. The OCDS interface allows application debugging and programming of on-board Flash ROM devices. The Infineon XC16x device should be wired to the OCDS connector pins as described in the following table.

Pin Connected to ...
TMS TMS pin; use 10KOhm pull-up resistor to VCC
TDO TDO pin
CPUCLK not used on KEIL ULINK
TDI TDI pin; use 10KOhm pull-up resistor to VCC
TRST TRST/ pin; use 10KOhm pull-up resistor to VCC
TCK TCK pin; use 10KOhm pull-up resistor to VCC
BRKIN BRKIN pin; use 10KOhm pull-up resistor to VCC
not used on KEIL ULINK
TRAP not used on C161U, C165H, C165UTAH
VCC Supply Voltage (+3.3V)
GND Digital Ground
RESET RSTIN/ pin; use 10KOhm pull-up resistor to VCC
BRKOUT BRKOUT pin
OCDS not used on C161U, C165H, C165UTAH

The pins TRST and RESET are open collector outputs on KEIL ULINK with 10KOhm pull-up resistor to 3,3V (VCC).

OCDS Driver for C16xU/H/UTAH - Settings

When you have selected Use: OCDS Driver for C16xU/H/UTAH under Project — Options for Target — Debug you can open the Settings dialog. The Settings dialog of the OCDS Driver for C16xU/H/UTAH allows you to configure device-specific options.

OCDS Driver Settings for C16xU/H/UTAH

JTAG Interface

Select LPT Printer Port or Keil ULINK (USB Adapter). If your computer has multiple ULINK adapters connected you need to select the serial number of the ULINK interface you want to use for debugging.

Monitor Configuration

For Infineon C161U, C165H, C165UTAH devices the µVision Debugger needs a small monitor program on the target system to support read/write access to the program counter (PC $). You can enter the start address of this monitor here. This monitor requires the DEBUG TRAP 8 (interrupt vector address 0x20 .. 0x23) and about 100 bytes of code. You need to reserve the DEBUG TRAP 8 (address range 0x20 - 0x23) of in your application with the Linker/Locater RESERVE directive. Under µVision the range 0x20 - 0x23 can be entered under Project - Options for Target - L166 Misc - Reserve.

Cache Options

These controls improve the performance of the µVision Debugger during target debugging by caching target memory areas in the PC memory. By default, these options are enabled to get maximum performance.

  • Ignore Code Modifications informs the debugger that the downloaded program code will not changed. µVision will therefore never read the program code from the target system. Disable this option if you are using self modifying code or if you have the impression that the program code is overwritten in your application.
  • Cache Memory selects that the memory content is considered to be unmodified during a program stop until the next single step, procedure step or go command is executed. Disable this option if you want to see the actual memory content (for example the data content of memory mapped peripherals) even if the debugger is halted.
  • Cache SFR Space is the same as Cache Memory for the SFR memory area 0xF000 – 0xF1FF and 0xFE00 – 0xFFFF.

Reset Configuration

To download application or monitor code into external memory devices it is required to initialize the external BUS system. This dialog section allows you to enter values for the SYSCON, BUSCONx and ADDRSELx registers. This registers will be directly initialized with OCDS commands to enable external memory devices.

Known Problems with OCDS on C161U, C165H, C165UTAH Devices

  • The current device versions require an valid CPU instruction at reset address 0 to stop the CPU after a reset. This is because the chip will go into HALT state only after execution of the first instruction. In most hardware designs, there is Flash ROM connected to chip select 0 (CS0) and RAM to chip select 1 (CS1). Therefore, the first instruction in ROM must be a valid instruction that does not cause any hardware traps or system lock up. The Infineon EASY UTAH board is shipped with a preprogrammed Flash ROM that does not cause such a problem. Also erased EPROM or Flash ROM devices will not cause a problem. Problems may arise only, when no device is active on the BUS at address 0 or when the ROM device contains random data.
  • When you download and start your application in external RAM that is not connected to chip select 0 (CS0) and you press the reset button on the target system, the system crashes. This is because only chip select 0 is active after a CPU reset and the RAM cannot be accessed in this case. There is no problem when you use the Reset command of the µVision Debugger.
  • When starting the µVision Debugger, the OCDS initialization time of the EASY UTAH board is very long (about 5 seconds) because the JTAG reset signal is delayed with a MAX 707 reset circuit.
  Arm logo
Important information

This site uses cookies to store information on your computer. By continuing to use our site, you consent to our cookies.

Change Settings

Privacy Policy Update

Arm’s Privacy Policy has been updated. By continuing to use our site, you consent to Arm’s Privacy Policy. Please review our Privacy Policy to learn more about our collection, use and transfers
of your data.