List of the armasm error and warning messages

--predefine "versionnum SETA 5"

--predefine "versionstr SETS \"5A\""

• The given name is not valid.
• There is no space.
• A read-only file with the same name already exists.
• The file is in use by another process.

stmib sp, {r0-r14}^ ; Return a pointer to the frame in a1.
mov r0, sp

stmib sp, {r0-r14}^ ; Return a pointer to the frame in a1.
nop
mov r0, sp

AREA 1_DataArea, CODE, READONLY

AREA |1_DataArea|, CODE, READONLY

ADD r0, r0, r1 comment

ADD r0, r0, r1 ; comment

IMPORT sym1
IMPORT sym2
DCD (sym2 - sym1)

• When the current file requires an INCLUDE of another file to define some symbols, for example:

  "init.s", line 2: Error: A1150E: Bad symbol
  2 00000000 DCD EBI_CSR_0
  

  In this case, the solution is to include the required definitions file. For example:

  INCLUDE targets/eb40.inc
  

• When the current file requires IMPORT for some symbols, for example:

  "init.s", line 4: Error: A1150E: Bad symbol
  4 00000000 LDR r0, =||Image$$RAM$$ZI$$Limit||
  

  In this case, the solution is to import the required symbol, for example:

  IMPORT ||Image$$RAM$$ZI$$Limit||
  

MCR p14, 3, R0, Cr1, Cr2

MCR p14, 3, r0, c1, c2

MCR p14, 3, R0, c1, c2

my_func FUNCTION

label SETS

• Forgetting to put white space in the left hand margin, before the instruction. For example, change the following:

  MOV PC,LR
  

  to:

   MOV PC,LR
  

• Use of a hardware floating point instruction without using the --fpu switch. For example:

   FMXR FPEXC, r1 ;
  

  must be assembled with armasm --fpu=vfp
• Mis-typing the opcode:

   ADDD
  

  instead of:

   ADD
  

• DCB.
• DCW and DCWU.

armasm init.s -g -PD "ROM_RAM_REMAP SETL {FALS}"

armasm init.s -g -PD "ROM_RAM_REMAP SETL {FALSE}"

AREA test,CODE,READONLY,HALFWORD

 MRS r0, PSR

 MRS r0, CPSR

 LDRH R3, =constant

MRS r0, CPSR_c

• Load addresses to a register using LDR Rd, =label.
• LTORG.

AREA Example, CODE
LDR pc, [pc, #6] ; Error – offset must be a multiple of 4
END

• If <Rn> is the lowest-numbered register specified in <register_list>, the original value of <Rn> is stored.
• Otherwise, the stored value of <Rn> is UNKNOWN.

 SUB sp, sp,#4
 STMID sp, {r0}^ 

 SUB r0, r0,#8
 STM r0, {r13, r14}^ 

    IF :DEF: FOO 
    ; code 
    ENDIF 

IF :DEF: FOO 
 ; code 
ENDIF 

 SMULBB r0,r0,r1 ;

armasm --cpu 5TE

• FRAME RESTORE.
• FRAME SAVE.

 AREA test1, CODE, READONLY 

 AREA test, CODE, READONLY, INTERWORK 

• remove the ", INTERWORK" from the AREA line.
• assemble with armasm --apcs /interwork foo.s instead.

 MRS(cond) Rd, CPSR 
 MRS(cond) Rd, SPSR 
 MSR(cond) CPSR_fields, Rm 
 MSR(cond) SPSR_fields, Rm 
 MSR(cond) CPSR_fields, #immediate 
 MSR(cond) SPSR_fields, #immediate 

• cpsr or cpsr_all, control and flags field
• cpsr_flg, flags field only
• cpsr_ctl, control field only.

Deprecated form of PSR field specifier used (use _cxsf)

• Conditional execution in ARM state.
• Conditional execution in Thumb state.
• General-purpose registers.
• Access to the inline barrel shifter.

• Frame directives.
• FRAME STATE REMEMBER.
• FRAME STATE RESTORE.

 AREA test, CODE, READONLY, INTERWORK

1. Remove the ", INTERWORK" from the AREA line.
2. Assemble with armasm --apcs /interwork foo.s instead.

 AREA test1, CODE, READONLY
   …
 AREA test2, CODE, READONLY, INTERWORK

1. Move the two AREAs into separate assembly files, for example, test1.s and test2.s.
2. Remove , INTERWORK from the AREA line in test2.s.
3. Assemble test1.s with armasm --apcs /nointerwork.
4. Assemble test2.s with armasm --apcs /interwork.
5. At link time, the linker adds any necessary interworking veneers.

armasm --cpu 4 code.s

• Modify the code to make the evaluation order explicit, by adding brackets.
• Suppress the warning with the --unsafe switch.

• Frame directives.
• FRAME STATE REMEMBER.
• FRAME STATE RESTORE.

  B unique_label
  LTORG
unique_label

ADD sp, r0, #100 ; error - UNPREDICTABLE use of SP
CMP pc, #1 ; error - UNPREDICTABLE use of PC
PUSH    {r0, pc} ; error - use of an UNPREDICTABLE register combination

 AREA test, CODE, ALIGN=3
 ALIGN 16
 mov pc, lr
 END

• a four-byte boundary for ARM code, so use "ALIGN=2"
• a two-byte boundary for Thumb code, so use "ALIGN=1".

• ALIGN.
• AREA.

• ROR.
• ASR.
• LSR.
• LSL.

• --unsafe.
• ASR.

  AREA code, CODE
 codeaddr DCD codeaddr
  END

  AREA data, DATA
 dataaddr DCD dataaddr
  END

 ADD r0, r0, r1

 ADD r0, r0, r1, ASR #1

PUSH {r0}

PUSH {r0,r1}

• --diag_warning=tag{, tag}.
• REQUIRE8 and PRESERVE8.

PRESERVE8
STRD r0,[sp,#8]

PRESERVE8 {FALSE}
REQUIRE8
STRD r0,[sp,#8]

 AREA Test, CODE, READONLY
 THUMB
ThumbCode
 MOVS r0, #1
 ADR r1, ARMProg
 BX r1
 ; ALIGN ; <<< uncomment to avoid the first warning
 ARM
ARMProg
 ADD r0,r0,#1
 BX LR
 DCB 0xFF
 DCD 0x1234
 END

A1581W: Added 2 bytes of padding at address 0x6
8 00000008 ARM
A1581W: Added 3 bytes of padding at address 0x11
13 00000014 DCD 0x1234

• ADR (PC-relative).
• ADR (register-relative).
• ALIGN.
• DCB.
• DCD and DCDU.

 MOV r0, pc
 ADDS r0, #1

--diag_suppress 1609

MOV r0, #1 ; /* Not permitted */
MOVS r0, #1 ; /* Ok */

• ADD negative_number is the same as SUB positive_number
• MOV negative_number is the same as MVN positive_number
• CMP negative_number is the same as CMN positive_number.

 AREA foo, CODE
 ADD r0, #-1
 MOV r0, #-1
 CMP r0, #-1

Warning: A1645W: Substituted ADD with SUB
3 00000000 ADD r0, #-1
Warning: A1645W: Substituted MOV with MVN
4 00000004 MOV r0, #-1
Warning: A1645W: Substituted CMP with CMN
5 00000008 CMP r0, #-1

foo
0x00000000: e2400001 ..@. SUB r0,r0,#1
0x00000004: e3e00000 .... MVN r0,#0
0x00000008: e3700001 ..p. CMN r0,#1

• You are using a deprecated register combination, for example:

  PUSH    {r0, pc}

• You are assembling for a target architecture that supports 32-bit Thumb instructions, in other words ARMv6T2 or later.
• You are assembling to ARM code.

 MOVEQ r0,r1

• You explicitly use the SP in a deprecated way, for example:

  ADD sp, r0, #100
  

• You are assembling for a target architecture that supports 32-bit Thumb instructions, in other words ARMv6T2 or later.
• You are assembling to ARM code.

ADD r1, r0, #100
MOV sp, r1

• You explicitly use the PC in a deprecated way, for example:

  CMP pc, #1
  

• You are assembling for a target architecture that supports 32-bit Thumb instructions, in other words ARMv6T2 or later.
• You are assembling to ARM code.

LDM r0!, {r0-r4}

LDM r0, {r0-r4}

• You are using a PC-relative offset in a Thumb instruction that requires the PC to be word-aligned.
• The code section containing this instruction has less than 4-byte alignment.
• The instruction is not relocated at link time (because of a relocation emitted by the assembler).

AREA ||.text||, CODE, READONLY, ALIGN=1
THUMB
LDR r0, [pc, #8]  ; gives warning A1809W

LDR r0, [pc, #label - . - 8]

LDR r0, [pc, #label-{PC}-8]

LDR r0, label

  ADDS    r0, r1, #-20

  SUBS    r0, r1, #20

    AREA x,CODE
    [ :DEF: foo
num EQU 42 ; Assembler does not see this line during pass 1 because
           ; foo is not defined at this point during pass 1
    ]
foo DCD num
    END

    map 0, r0
    if :lnot: :def: sym
        map 0, r9
        field 4
    endif
x   field 4
sym LDR r0, x

    AREA x,CODE
    [ :LNOT: :DEF: foo
    MOV r1, r2  ; Assembler does not see this line during pass 2 because
                ; foo is already defined
    ]
foo MOV r3, r4
    END