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Home / Compiler Reference Guide Version 6.15
--coprocN=value (fromelf)
D1.10 --coprocN=value (fromelf)
Enables T32 encodings of the Custom Datapath Extension (CDE). These options are only compatible with M-profile targets and require the target to support at least Arm®v8‑M mainline.
Syntax
--coprocN =value
Where N is the coprocessor ID in the range 0-7, and value is one of the following:
generic
- This value is the default, and has the same effect as if
--coprocN
is omitted.
cde , CDE
- Sets the instruction set architecture of the corresponding coprocessor encoding space to CDEv1.
Restrictions
You must use the --cpu option with --coprocN =value
.
Example: CDE instructions with vector operands
-
Create the file cde-vector.S that uses coprocessor 0:
.text
.global f
f:
vcx1a p0, q1, #1
vcx1 p0, q2, #1
vcx2a p0, q1, q2, #1
vcx2 p0, q2, q3, #1
vcx3a p0, q1, q2, q3, #1
vcx3 p0, q1, q3, q4, #1
-
Compile cde-vector.S with:
armclang -target arm-arm-none-eabi -march=armv8-m.main+cdecp0+mve -mfpu=fpv5-sp-d16 -c cde-vector.S
-
Run fromelf to examine the generated assembly code:
fromelf -c --cpu=8-M.Main --coproc0=cde cde-vector.o
...
f
0x00000000: fc202041 .A VCX1A p0,q1,#1
0x00000004: ec204041 .A@ VCX1 p0,q2,#1
0x00000008: fc302054 0.T VCX2A p0,q1,q2,#1
0x0000000c: ec304056 0.V@ VCX2 p0,q2,q3,#1
0x00000010: fc842056 ..V VCX3A p0,q1,q2,q3,#1
0x00000014: ec862058 ..X VCX3 p0,q1,q3,q4,#1
...
If you do not specify a required feature, then the following errors are output:
-
If you do not enable the CDE extension for a particular coprocessor, then you get errors such as:
armclang.exe --target=arm-arm-none-eabi -march=armv8-m.main+mve -mfpu=fpv5-sp-d16 -c cde-vector.S
cde-vector.S:5:8: error: coprocessor must be configured as CDE
vcx1a p0, q1, #1
...
-
If you do not enable M-profile Vector Extension (MVE), then you get errors such as:
armclang.exe --target=arm-arm-none-eabi -march=armv8-m.main+cdecp0 -mfpu=fpv5-sp-d16 -c cde-vector.S
cde-vector.S:5:2: error: invalid instruction, any one of the following would fix this:
vcx1a p0, q1, #1
^
cde-vector.S:5:12: note: operand must be a register in range [s0, s31]
vcx1a p0, q1, #1
^
cde-vector.S:5:2: note: instruction requires: mve
vcx1a p0, q1, #1
^
...
-
If you do not enable an FPU with -mfpu=none , then you get an error for floating-point instructions, for example:
armclang.exe --target=arm-arm-none-eabi -march=armv8-m.main -mfpu=none -c cde-vector.S
cde-vector.S:5:2: error: invalid instruction
vcx1a p0, q1, #1
^
...
Note: Enabling MVE causes single-precision, double-precision, and vector registers to be available for CDE instructions, even if FPU is disabled.
-
If you do not specify the --coproc0=cde option, then the disassmbly has LDC and STC instructions instead of the expected VCX instructions. For example:
fromelf -c --cpu=8-M.Main cde-vector.o
...
f
0x00000000: fc202041 .A STC2 p0,c2,[r0],#-0x104
0x00000004: ec204041 .A@ STC p0,c4,[r0],#-0x104
0x00000008: fc302054 0.T LDC2 p0,c2,[r0],#-0x150
0x0000000c: ec304056 0.V@ LDC p0,c4,[r0],#-0x158
0x00000010: fc842056 ..V STC2 p0,c2,[r4],{0x56}
0x00000014: ec862058 ..X STC p0,c2,[r6],{0x58}
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