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Preface Arm Compiler Tools Overview armclang Reference armlink Reference fromelf Reference armar Reference armasm Legacy Assembler Reference armasm Command-line Options --16 --32 --apcs=qualifier…qualifier --arm --arm_only --bi --bigend --brief_diagnostics, --no_brief_diagnostics --checkreglist --cpreproc --cpreproc_opts=option[,option,…] --cpu=list (armasm) --cpu=name (armasm) --debug --depend=dependfile --depend_format=string --diag_error=tag[,tag,…] (armasm) --diag_remark=tag[,tag,…] (armasm) --diag_style={arm|ide|gnu} (armasm) --diag_suppress=tag[,tag,…] (armasm) --diag_warning=tag[,tag,…] (armasm) --dllexport_all --dwarf2 --dwarf3 --errors=errorfile --exceptions, --no_exceptions --exceptions_unwind, --no_exceptions_unwind --execstack, --no_execstack --execute_only --fpmode=model --fpu=list (armasm) --fpu=name (armasm) -g (armasm) --help (armasm) -idir[,dir, …] --keep (armasm) --length=n --li --library_type=lib --list=file --list= --littleend -m (armasm) --maxcache=n --md --no_code_gen --no_esc --no_hide_all --no_regs --no_terse --no_warn -o filename (armasm) --pd --predefine "directive" --reduce_paths, --no_reduce_paths --regnames --report-if-not-wysiwyg --show_cmdline (armasm) --thumb --unaligned_access, --no_unaligned_access --unsafe --untyped_local_labels --version_number (armasm) --via=filename (armasm) --vsn (armasm) --width=n --xref Structure of armasm Assembly Language Modules Syntax of source lines in armasm syntax assembly l Literals ELF sections and the AREA directive An example armasm syntax assembly language module Writing A32/T32 Instructions in armasm Syntax Asse About the Unified Assembler Language Syntax differences between UAL and A64 assembly la Register usage in subroutine calls Load immediate values Load immediate values using MOV and MVN Load immediate values using MOV32 Load immediate values using LDR Rd, =const Literal pools Load addresses into registers Load addresses to a register using ADR Load addresses to a register using ADRL Load addresses to a register using LDR Rd, =label Other ways to load and store registers Load and store multiple register instructions Load and store multiple register instructions in A Stack implementation using LDM and STM Stack operations for nested subroutines Block copy with LDM and STM Memory accesses The Read-Modify-Write operation Optional hash with immediate constants Use of macros Test-and-branch macro example Unsigned integer division macro example Instruction and directive relocations Symbol versions Frame directives Exception tables and Unwind tables Using armasm armasm command-line syntax Specify command-line options with an environment v Using stdin to input source code to the assembler Built-in variables and constants Identifying versions of armasm in source code Diagnostic messages Interlocks diagnostics Automatic IT block generation in T32 code T32 branch target alignment T32 code size diagnostics A32 and T32 instruction portability diagnostics T32 instruction width diagnostics Two pass assembler diagnostics Using the C preprocessor Address alignment in A32/T32 code Address alignment in A64 code Instruction width selection in T32 code Symbols, Literals, Expressions, and Operators in a Symbol naming rules Variables Numeric constants Assembly time substitution of variables Register-relative and PC-relative expressions Labels Labels for PC-relative addresses Labels for register-relative addresses Labels for absolute addresses Numeric local labels Syntax of numeric local labels String expressions String literals Numeric expressions Syntax of numeric literals Syntax of floating-point literals Logical expressions Logical literals Unary operators Binary operators Multiplicative operators String manipulation operators Shift operators Addition, subtraction, and logical operators Relational operators Boolean operators Operator precedence Difference between operator precedence in assembly armasm Directives Reference Alphabetical list of directives armasm assembly la About armasm assembly language control directives About frame directives Directives that can be omitted in pass 2 of the as ALIAS ALIGN AREA ARM or CODE32 directive ASSERT ATTR CN CODE16 directive COMMON CP DATA DCB DCD and DCDU DCDO DCFD and DCFDU DCFS and DCFSU DCI DCQ and DCQU DCW and DCWU END ENDFUNC or ENDP ENTRY EQU EXPORT or GLOBAL EXPORTAS FIELD FRAME ADDRESS FRAME POP FRAME PUSH FRAME REGISTER FRAME RESTORE FRAME RETURN ADDRESS FRAME SAVE FRAME STATE REMEMBER FRAME STATE RESTORE FRAME UNWIND ON FRAME UNWIND OFF FUNCTION or PROC GBLA, GBLL, and GBLS GET or INCLUDE IF, ELSE, ENDIF, and ELIF IMPORT and EXTERN INCBIN INFO KEEP LCLA, LCLL, and LCLS LTORG MACRO and MEND MAP MEXIT NOFP OPT QN, DN, and SN RELOC REQUIRE REQUIRE8 and PRESERVE8 RLIST RN ROUT SETA, SETL, and SETS SPACE or FILL THUMB directive TTL and SUBT WHILE and WEND WN and XN armasm-Specific A32 and T32 Instruction Set Featur armasm support for the CSDB instruction A32 and T32 pseudo-instruction summary ADRL pseudo-instruction CPY pseudo-instruction LDR pseudo-instruction MOV32 pseudo-instruction NEG pseudo-instruction UND pseudo-instruction Appendixes

Load addresses to a register using LDR Rd, =label

F3.12 Load addresses to a register using LDR Rd, =label

The LDR Rd,=label pseudo-instruction places an address in a literal pool and then loads the address into a register.

LDR Rd,=label can load any 32-bit numeric value into a register. It also accepts PC-relative expressions such as labels, and labels with offsets.

The assembler converts an LDR Rd,=label pseudo-instruction by:

  • Placing the address of label in a literal pool (a portion of memory embedded in the code to hold constant values).
  • Generating a PC-relative LDR instruction that reads the address from the literal pool, for example:
        LDR rn [pc, #offset_to_literal_pool]
                            ; load register n with one word
                            ; from the address [pc + offset]

    You must ensure that the literal pool is within range of the LDR pseudo-instruction that needs to access it.

Example of loading using LDR Rd, =label

The following example shows a section with two literal pools. The final LDR pseudo-instruction needs to access the second literal pool, but it is out of range. Uncommenting this line causes the assembler to generate an error.

The instructions listed in the comments are the A32 instructions generated by the assembler.

        AREA   LDRlabel, CODE, READONLY
        ENTRY                     ; Mark first instruction to execute
        BL     func1              ; Branch to first subroutine
        BL     func2              ; Branch to second subroutine
        MOV    r0, #0x18          ; angel_SWIreason_ReportException
        LDR    r1, =0x20026       ; ADP_Stopped_ApplicationExit
        SVC    #0x123456          ; AArch32 semihosting (formerly SWI)
        LDR    r0, =start         ; => LDR r0,[PC, #offset into Literal Pool 1]
        LDR    r1, =Darea + 12    ; => LDR r1,[PC, #offset into Literal Pool 1]
        LDR    r2, =Darea + 6000  ; => LDR r2,[PC, #offset into Literal Pool 1]
        BX     lr                 ; Return
        LTORG                     ; Literal Pool 1
        LDR    r3, =Darea + 6000  ; => LDR r3,[PC, #offset into Literal Pool 1]
                                  ; (sharing with previous literal)
        ; LDR   r4, =Darea + 6004 ; If uncommented, produces an error because
                                  ; Literal Pool 2 is out of range.
        BX     lr                 ; Return
Darea   SPACE  8000               ; Starting at the current location, clears 
                                  ; a 8000 byte area of memory to zero.
        END                       ; Literal Pool 2 is automatically inserted 
                                  ; after the END directive. 
                                  ; It is out of range of all the LDR
                                  ; pseudo-instructions in this example.

Example of string copy

The following example shows an A32 code routine that overwrites one string with another. It uses the LDR pseudo-instruction to load the addresses of the two strings from a data section. The following are particularly significant:


The DCB directive defines one or more bytes of store. In addition to integer values, DCB accepts quoted strings. Each character of the string is placed in a consecutive byte.


The LDR and STR instructions use post-indexed addressing to update their address registers. For example, the instruction:

LDRB    r2,[r1],#1

loads R2 with the contents of the address pointed to by R1 and then increments R1 by 1.

The example also shows how, unlike the ADR and ADRL pseudo-instructions, you can use the LDR pseudo-instruction with labels that are outside the current section. The assembler places a relocation directive in the object code when the source file is assembled. The relocation directive instructs the linker to resolve the address at link time. The address remains valid wherever the linker places the section containing the LDR and the literal pool.

        AREA    StrCopy, CODE, READONLY
        ENTRY                       ; Mark first instruction to execute
        LDR     r1, =srcstr         ; Pointer to first string
        LDR     r0, =dststr         ; Pointer to second string
        BL      strcopy             ; Call subroutine to do copy
        MOV     r0, #0x18           ; angel_SWIreason_ReportException
        LDR     r1, =0x20026        ; ADP_Stopped_ApplicationExit
        SVC     #0x123456           ; AArch32 semihosting (formerly SWI)
        LDRB    r2, [r1],#1         ; Load byte and update address
        STRB    r2, [r0],#1         ; Store byte and update address
        CMP     r2, #0              ; Check for zero terminator
        BNE     strcopy             ; Keep going if not
        MOV     pc,lr               ; Return
        AREA    Strings, DATA, READWRITE
srcstr  DCB     "First string - source",0
dststr  DCB     "Second string - destination",0
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