Arm® Compiler does not guarantee that a single-copy atomic instruction is used to access a volatile variable that is larger than the natural architecture data size, even when one is available for the target processor.
When compiling for AArch64 state, the natural architecture data size is 64-bits. Targets such as the Cortex®‑A53 processor support single-copy atomic instructions for 128-bit data types. In this case, you might expect the compiler to generate an instruction with single-copy atomicity to access a volatile 128-bit variable. However, the architecture does not guarantee single-copy atomicity access. Therefore, the compiler does not support it.
When compiling for AArch32 state, the natural architecture data size is 32-bits. In this case, you might expect the compiler to generate an instruction with single-copy atomicity to access a volatile 64-bit variable. However, the architecture does not guarantee single-copy atomicity access. Therefore, the compiler does not support it.
Arm’s Privacy Policy has been updated. By continuing to use our site, you consent to Arm’s Privacy Policy. Please review our Privacy Policy to learn more about our collection, use and transfers of your data.