Technical Support
On-Line Manuals
Compiler Reference Guide
Preface
Arm Compiler Tools Overview
armclang Reference
armclang Command-line Options
Summary of armclang command-line options
-C (armclang)
-c (armclang)
-D
-E
-e
-fbare-metal-pie
-fbracket-depth=N
-fcommon, -fno-common
-fdata-sections, -fno-data-sections
-ffast-math, -fno-fast-math
-ffixed-rN
-ffp-mode
-ffunction-sections, -fno-function-sections
-fident, -fno-ident
@file
-fldm-stm, -fno-ldm-stm
-fno-builtin
-fno-inline-functions
-flto, -fno-lto
-fexceptions, -fno-exceptions
-fomit-frame-pointer, -fno-omit-frame-pointer
-fpic, -fno-pic
-fropi, -fno-ropi
-fropi-lowering, -fno-ropi-lowering
-frwpi, -fno-rwpi
-frwpi-lowering, -fno-rwpi-lowering
-fsanitize
-fshort-enums, -fno-short-enums
-fshort-wchar, -fno-short-wchar
-fstack-protector, -fstack-protector-all, -fstack-
-fstrict-aliasing, -fno-strict-aliasing
-fsysv, -fno-sysv
-ftrapv
-fvectorize, -fno-vectorize
-fvisibility
-fwrapv
-g, -gdwarf-2, -gdwarf-3, -gdwarf-4 (armclang)
-I
-include
-L
-l
-M, -MM
-MD, -MMD
-MF
-MG
-MP
-MT
-march
-marm
-masm
-mbig-endian
-mbranch-protection
-mcmodel
-mcmse
-mcpu
-mexecute-only
-mfloat-abi
-mfpu
-mimplicit-it
-mlittle-endian
-mno-neg-immediates
-moutline, -mno-outline
-mpixolib
-munaligned-access, -mno-unaligned-access
-mthumb
-nostdlib
-nostdlibinc
-O (armclang)
-o (armclang)
-pedantic
-pedantic-errors
-Rpass
-S
-save-temps
-shared (armclang)
-std
--target
-U
-u (armclang)
-v (armclang)
--version (armclang)
--version_number (armclang)
--vsn (armclang)
-W
-Wl
-Xlinker
-x (armclang)
-###
Compiler-specific Keywords and Operators
Compiler-specific keywords and operators
__alignof__
__asm
__declspec attributes
__declspec(noinline)
__declspec(noreturn)
__declspec(nothrow)
__inline
__promise
__unaligned
Global named register variables
Compiler-specific Function, Variable, and Type Att
Function attributes
__attribute__((always_inline)) function attribute
__attribute__((cmse_nonsecure_call)) function attr
__attribute__((cmse_nonsecure_entry)) function att
__attribute__((const)) function attribute
__attribute__((constructor(priority))) function at
__attribute__((format_arg(string-index))) function
__attribute__((interrupt("type"))) function attrib
__attribute__((malloc)) function attribute
__attribute__((naked)) function attribute
__attribute__((noinline)) function attribute
__attribute__((nonnull)) function attribute
__attribute__((noreturn)) function attribute
__attribute__((nothrow)) function attribute
__attribute__((pcs("calling_convention"))) functio
__attribute__((pure)) function attribute
__attribute__((section("name"))) function attribut
__attribute__((target("options"))) function attrib
__attribute__((unused)) function attribute
__attribute__((used)) function attribute
__attribute__((value_in_regs)) function attribute
__attribute__((visibility("visibility_type"))) fun
__attribute__((weak)) function attribute
__attribute__((weakref("target"))) function attrib
Type attributes
__attribute__((aligned)) type attribute
__attribute__((packed)) type attribute
__attribute__((transparent_union)) type attribute
Variable attributes
__attribute__((alias)) variable attribute
__attribute__((aligned)) variable attribute
__attribute__((deprecated)) variable attribute
__attribute__((packed)) variable attribute
__attribute__((section("name"))) variable attribut
__attribute__((unused)) variable attribute
__attribute__((used)) variable attribute
__attribute__((visibility("visibility_type"))) var
__attribute__((weak)) variable attribute
__attribute__((weakref("target"))) variable attrib
Compiler-specific Intrinsics
__breakpoint intrinsic
__current_pc intrinsic
__current_sp intrinsic
__disable_fiq intrinsic
__disable_irq intrinsic
__enable_fiq intrinsic
__enable_irq intrinsic
__force_stores intrinsic
__memory_changed intrinsic
__schedule_barrier intrinsic
__semihost intrinsic
__vfp_status intrinsic
Compiler-specific Pragmas
#pragma clang system_header
#pragma clang diagnostic
#pragma clang section
#pragma once
#pragma pack(...)
#pragma unroll[(n)], #pragma unroll_completely
#pragma weak symbol, #pragma weak symbol1 = symbol
Other Compiler-specific Features
ACLE support
Predefined macros
Inline functions
Volatile variables
Half-precision floating-point data types
Half-precision floating-point number format
Half-precision floating-point intrinsics
Library support for _Float16 data type
BFloat16 floating-point number format
TT instruction intrinsics
Non-secure function pointer intrinsics
Supported architecture feature combinations for sp
armclang Integrated Assembler
Syntax of assembly files for integrated assembler
Assembly expressions
Alignment directives
Data definition directives
String definition directives
Floating-point data definition directives
Section directives
Conditional assembly directives
Macro directives
Symbol binding directives
Org directive
AArch32 Target selection directives
AArch64 Target selection directives
Space-filling directives
Type directive
Integrated assembler support for the CSDB instruct
armclang Inline Assembler
Inline Assembly
File-scope inline assembly
Inline assembly statements within a function
Assembly string
Output and input operands
Clobber list
volatile
Inline assembly constraint strings
Constraint modifiers
Constraint codes
Constraint codes common to AArch32 state and AArch
Constraint codes for AArch32 state
Constraint codes for AArch64 state
Using multiple alternative operand constraints
Inline assembly template modifiers
Template modifiers common to AArch32 state and AAr
Template modifiers for AArch32 state
Template modifiers for AArch64 state
Forcing inline assembly operands into specific reg
Symbol references and branches into and out of inl
Duplication of labels in inline assembly statement
armlink Reference
fromelf Reference
armar Reference
armasm Legacy Assembler Reference
Appendixes
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Home / Compiler Reference Guide Version 6.15
-mfpu
B1.59 -mfpu
Specifies the target FPU architecture, that is the floating-point hardware available on the target.
Syntax
To view a list of all the supported FPU architectures, use:
-mfpu=list
Note: -mfpu=list is rejected when targeting
AArch64 state.
Alternatively, to specify a target FPU architecture, use:
-mfpu=name
Where name is one of the following:
none , softvfp
- Use either
-mfpu=none or
-mfpu=softvfp to prevent the compiler from using
hardware-based floating-point functions. If the compiler encounters
floating-point types in the source code, it uses software-based
floating-point library functions. This option is similar to the -mfloat-abi=soft option.
vfpv3
- Enable the Arm®v7 VFPv3 Floating-point Extension. Disable the Advanced SIMD extension.
vfpv3-d16
- Enable the Armv7 VFPv3-D16 Floating-point Extension. Disable the Advanced SIMD extension.
vfpv3-fp16
- Enable the Armv7 VFPv3 Floating-point Extension, including the optional half-precision extensions. Disable the Advanced SIMD extension.
vfpv3-d16-fp16
- Enable the Armv7 VFPv3-D16 Floating-point Extension, including the optional half-precision extensions. Disable the Advanced SIMD extension.
vfpv3xd
- Enable the Armv7 VFPv3XD Floating-point Extension, for single
precision only. Disable the Advanced SIMD extension.
vfpv3xd-fp16
- Enable the Armv7 VFPv3XD Floating-point Extension, for single
precision (including the optional half-precision extensions). Disable the
Advanced SIMD extension.
neon
- Enable the Armv7 VFPv3 Floating-point Extension and the Advanced SIMD extension.
neon-fp16
- Enable the Armv7 VFPv3 Floating-point Extension, including the optional half-precision extensions, and the Advanced SIMD extension.
vfpv4
- Enable the Armv7 VFPv4 Floating-point Extension. Disable the Advanced SIMD extension.
vfpv4-d16
- Enable the Armv7 VFPv4-D16 Floating-point Extension. Disable the Advanced SIMD extension.
neon-vfpv4
- Enable the Armv7 VFPv4 Floating-point Extension and the Advanced SIMD extension.
fpv4-sp-d16
- Enable the Armv7 FPv4-SP-D16 Floating-point Extension for single
precision only.
fpv5-d16
- Enable the Armv7 FPv5-D16 Floating-point Extension. This option disables the scalar half-precision floating-point operations feature. Therefore, because the M-profile Vector Extension (MVE) floating-point feature requires the scalar half-precision floating-point operations, this option also disables the MVE floating-point feature,
+mve.fp . Arm recommends using the generic +fp and +fp.dp extension names instead of -mfpu . See B1.56 -mcpu and B6.12 Supported architecture feature combinations for specific processors for more information.
fpv5-sp-d16
- Enable the Armv7 FPv5-SP-D16 Floating-point Extension for single
precision only. This option disables the scalar half-precision
floating-point operations feature. Therefore, because the MVE floating-point
feature requires the scalar half-precision floating-point operations, this
option also disables the MVE floating-point feature,
+mve.fp . Arm
recommends using the generic +fp and
+fp.dp extension names instead of
-mfpu . See B1.56 -mcpu and B6.12 Supported architecture feature combinations for specific processors for more
information.
fp-armv8
- Enable the Armv8 Floating-point Extension. Disable the Cryptographic Extension and the Advanced SIMD extension.
neon-fp-armv8
- Enable the Armv8 Floating-point Extension and the Advanced SIMD extensions. Disable the Cryptographic Extension.
crypto-neon-fp-armv8
- Enable the Armv8 Floating-point Extension, the Cryptographic Extension, and the Advanced SIMD extension.
The -mfpu option overrides the default FPU
option implied by the target architecture.
Note:
- The
-mfpu option is ignored
with AArch64 targets, for example aarch64-arm-none-eabi . Use the -mcpu option to override the default FPU for aarch64-arm-none-eabi targets. For example, to
prevent the use of floating-point instructions or floating-point registers
for the aarch64-arm-none-eabi target use
the -mcpu=name +nofp+nosimd option. Subsequent use of
floating-point data types in this mode is unsupported.
- In Armv7, the Advanced
SIMD extension was called the Arm Neon™ Advanced SIMD extension.
Note: There are no software floating-point libraries for targets in AArch64 state. When linking for targets in AArch64 state, armlink uses AArch64 libraries that contain Advanced SIMD and floating-point instructions and registers. The use of the AArch64 libraries applies even if you compile the source with -mcpu=<name>+nofp+nosimd to prevent the compiler from using Advanced SIMD and floating-point instructions and registers. Therefore, there is no guarantee that the linked image for targets in AArch64 state is entirely free of Advanced SIMD and floating-point instructions and registers.
You can prevent the use of Advanced SIMD and floating-point instructions and registers in images that are linked for targets in AArch64 state. Either re-implement the library functions or create your own library that does not use Advanced SIMD and floating-point instructions and registers.
Note: In AArch32 state, if you specify -mfloat-abi=soft , then specifying the -mfpu option does not have an effect.
Default
The default FPU option depends on the target processor.
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