-mfpu

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Arm^® Compiler Reference Guide

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B1.59 -mfpu

Specifies the target FPU architecture, that is the floating-point hardware available on the target.

Syntax

To view a list of all the supported FPU architectures, use:

-mfpu=list

Note:

-mfpu=list is rejected when targeting AArch64 state.

Alternatively, to specify a target FPU architecture, use:

-mfpu=name

Where name is one of the following:

none, softvfp: Use either -mfpu=none or -mfpu=softvfp to prevent the compiler from using hardware-based floating-point functions. If the compiler encounters floating-point types in the source code, it uses software-based floating-point library functions. This option is similar to the -mfloat-abi=soft option.
vfpv3: Enable the Arm^®v7 VFPv3 Floating-point Extension. Disable the Advanced SIMD extension.
vfpv3-d16: Enable the Armv7 VFPv3-D16 Floating-point Extension. Disable the Advanced SIMD extension.
vfpv3-fp16: Enable the Armv7 VFPv3 Floating-point Extension, including the optional half-precision extensions. Disable the Advanced SIMD extension.
vfpv3-d16-fp16: Enable the Armv7 VFPv3-D16 Floating-point Extension, including the optional half-precision extensions. Disable the Advanced SIMD extension.
vfpv3xd: Enable the Armv7 VFPv3XD Floating-point Extension, for single precision only. Disable the Advanced SIMD extension.
vfpv3xd-fp16: Enable the Armv7 VFPv3XD Floating-point Extension, for single precision (including the optional half-precision extensions). Disable the Advanced SIMD extension.
neon: Enable the Armv7 VFPv3 Floating-point Extension and the Advanced SIMD extension.
neon-fp16: Enable the Armv7 VFPv3 Floating-point Extension, including the optional half-precision extensions, and the Advanced SIMD extension.
vfpv4: Enable the Armv7 VFPv4 Floating-point Extension. Disable the Advanced SIMD extension.
vfpv4-d16: Enable the Armv7 VFPv4-D16 Floating-point Extension. Disable the Advanced SIMD extension.
neon-vfpv4: Enable the Armv7 VFPv4 Floating-point Extension and the Advanced SIMD extension.
fpv4-sp-d16: Enable the Armv7 FPv4-SP-D16 Floating-point Extension for single precision only.
fpv5-d16: Enable the Armv7 FPv5-D16 Floating-point Extension. This option disables the scalar half-precision floating-point operations feature. Therefore, because the M-profile Vector Extension (MVE) floating-point feature requires the scalar half-precision floating-point operations, this option also disables the MVE floating-point feature, +mve.fp. Arm recommends using the generic +fp and +fp.dp extension names instead of -mfpu. See B1.56 -mcpu and B6.12 Supported architecture feature combinations for specific processors for more information.
fpv5-sp-d16: Enable the Armv7 FPv5-SP-D16 Floating-point Extension for single precision only. This option disables the scalar half-precision floating-point operations feature. Therefore, because the MVE floating-point feature requires the scalar half-precision floating-point operations, this option also disables the MVE floating-point feature, +mve.fp. Arm recommends using the generic +fp and +fp.dp extension names instead of -mfpu. See B1.56 -mcpu and B6.12 Supported architecture feature combinations for specific processors for more information.
fp-armv8: Enable the Armv8 Floating-point Extension. Disable the Cryptographic Extension and the Advanced SIMD extension.
neon-fp-armv8: Enable the Armv8 Floating-point Extension and the Advanced SIMD extensions. Disable the Cryptographic Extension.
crypto-neon-fp-armv8: Enable the Armv8 Floating-point Extension, the Cryptographic Extension, and the Advanced SIMD extension.

The -mfpu option overrides the default FPU option implied by the target architecture.

Note:

The -mfpu option is ignored with AArch64 targets, for example aarch64-arm-none-eabi. Use the -mcpu option to override the default FPU for aarch64-arm-none-eabi targets. For example, to prevent the use of floating-point instructions or floating-point registers for the aarch64-arm-none-eabi target use the -mcpu=name+nofp+nosimd option. Subsequent use of floating-point data types in this mode is unsupported.
In Armv7, the Advanced SIMD extension was called the Arm Neon™ Advanced SIMD extension.

Note:

There are no software floating-point libraries for targets in AArch64 state. When linking for targets in AArch64 state, armlink uses AArch64 libraries that contain Advanced SIMD and floating-point instructions and registers. The use of the AArch64 libraries applies even if you compile the source with -mcpu=<name>+nofp+nosimd to prevent the compiler from using Advanced SIMD and floating-point instructions and registers. Therefore, there is no guarantee that the linked image for targets in AArch64 state is entirely free of Advanced SIMD and floating-point instructions and registers.

You can prevent the use of Advanced SIMD and floating-point instructions and registers in images that are linked for targets in AArch64 state. Either re-implement the library functions or create your own library that does not use Advanced SIMD and floating-point instructions and registers.