Template modifiers for AArch32 state

a

If the operand uses a register constraint, it is printed surrounded by square brackets. If it uses a constant constraint, it is printed as a plain immediate, with no preceding #.

y

The operand must be a 32-bit floating-point type, using a register constraint. It is printed as the equivalent D register with an index. For example, the register S2 is printed as d1[0], and the register S3 is printed as d1[1].

B

The operand must use a constant constraint, and is printed as the bitwise inverse of the value, without a preceding #.

L

The operand must use a constant constraint, and is printed as the least-significant 16 bits of the value, without a preceding #.

Q

The operand must use the r constraint, and must be a 64-bit integer or floating-point type. The operand is printed as the register holding the least-significant half of the value.

R

The operand must use the r constraint, and must be a 64-bit integer or floating-point type. The operand is printed as the register holding the most-significant half of the value.

H

The operand must use the r constraint, and must be a 64-bit integer or floating-point type. The operand is printed as the highest-numbered register holding half of the value.

e

The operand must be a 128-bit vector type, using the w or x constraint. The operand is printed as the D register that overlaps the low half of the allocated Q register.

f

The operand must be a 128-bit vector type, using the w or x constraint. The operand is printed as the D register that overlaps the high half of the allocated Q register.

m

The operand must use the m constraint, and is printed as a register without the surrounding square brackets.

Example

// In AArch32 state, the 'Q' and 'R' template modifiers can be used to print
// the registers holding the least- and most-significant half of a 64-bit
// operand.
uint64_t atomic_swap(uint64_t new_val, uint64_t *addr) {
	uint64_t old_val;
	unsigned temp;
	__asm volatile(
		  "dmb ish\n"
		  "1:\n"
		  "ldrexd %Q[old], %R[old], %[addr]\n"
		  "strexd %[temp], %Q[new], %R[new], %[addr]\n"
		  "cmp %[temp], #0\n"
		  "bne 1b\n"
		  "dmb ish\n"
		: [new] "+&r" (old_val),
		  [temp] "=&r" (temp)
		: [old] "r"   (new_val),
		  [addr] "m"  (*addr));
	return old_val;
}