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Inline functions
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Compiler support for floating-point arithmetic
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Vector Floating-Point (VFP) architectures
Limitations on hardware handling of floating-point
Implementation of Vector Floating-Point (VFP) supp
Compiler and library support for half-precision fl
Half-precision floating-point number format
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Integer division-by-zero errors in C code
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Software floating-point division-by-zero debugging
New language features of C99
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// comments in C99 and C90
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Compiler Diagnostic Messages
Using the Inline and Embedded Assemblers of the AR
Compiler Command-line Options
Language Extensions
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C and C++ Implementation Details
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Summary Table of GNU Language Extensions
Standard C Implementation Definition
Standard C++ Implementation Definition
C and C++ Compiler Implementation Limits
Vector Floating-Point (VFP) architectures
| Non-Confidential |  PDF version | ARM DUI0375H | ||
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| Home > Compiler Coding Practices > Vector Floating-Point (VFP) architectures | ||||
4.44 Vector Floating-Point (VFP) architectures
ARM supports several versions of the VFP architecture, implemented in different ARM architectures.
VFP architectures provide both single and double precision operations. Many operations can
take place in either scalar form or in vector form. Several versions of the architecture are
supported, including:
- VFPv2, implemented in:
- VFP9-S, available as a separately licensable option for the ARM926E, ARM946E and ARM966E processors.
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VFPv3, implemented on ARM architecture v7 and later. VFPv3 is backwards compatible with VFPv2, except that it cannot trap floating point exceptions. It requires no software support code. VFPv3 has 32 double-precision registers.
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VFPv3_fp16, VFPv3 with half-precision extensions. These extensions provide conversion functions between half-precision floating-point numbers and single-precision floating-point numbers, in both directions. They can be implemented with any VFP implementation that supports single-precision floating-point numbers.
- VFPv3U, an implementation of VFPv3 that can trap floating-point exceptions. It requires software support code.
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VFPv4, implemented on ARM architecture v7 and later. VFPv4 has 32 double-precision registers. VFPv4 adds both half-precision extensions and fused multiply-add instructions to the features of VFPv3.
- VFPv4U, an implementation of VFPv4 that can trap floating-point exceptions. It requires software support code.
Note
Particular implementations of the VFP architecture might provide additional implementation-specific functionality. For example, the VFP coprocessor hardware might include extra registers for describing exceptional conditions. This extra functionality is known as sub-architecture functionality.Related concepts
Related reference
Related information
| Non-Confidential | PDF version | ARM DUI0375H |
| Copyright © 2007, 2008, 2011, 2012, 2014-2016 ARM. All rights reserved. |
| Home > Compiler Coding Practices > Vector Floating-Point (VFP) architectures |
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