ARM supports several versions of the VFP architecture, implemented in different ARM architectures.
VFP architectures provide both single and double precision operations. Many operations can
take place in either scalar form or in vector form. Several versions of the architecture are
supported, including:
VFPv2, implemented in:
VFP9-S, available as a separately licensable option for the ARM926E, ARM946E and
ARM966E processors.
VFPv3, implemented on ARM architecture v7 and later. VFPv3 is backwards
compatible with VFPv2, except that it cannot trap floating point exceptions. It requires
no software support code. VFPv3 has 32 double-precision registers.
VFPv3_fp16, VFPv3 with half-precision extensions. These extensions
provide conversion functions between half-precision floating-point numbers and
single-precision floating-point numbers, in both directions. They can be implemented
with any VFP implementation that supports single-precision floating-point numbers.
VFPv3U, an implementation of VFPv3 that can trap floating-point exceptions. It
requires software support code.
VFPv4, implemented on ARM architecture v7 and later. VFPv4 has 32
double-precision registers. VFPv4 adds both half-precision extensions and fused
multiply-add instructions to the features of VFPv3.
VFPv4U, an implementation of VFPv4 that can trap floating-point exceptions. It
requires software support code.
Note
Particular implementations of the VFP architecture might provide additional
implementation-specific functionality. For example, the VFP coprocessor hardware might
include extra registers for describing exceptional conditions. This extra functionality is
known as sub-architecture functionality.
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