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Floating-point compare.


VCMP{E}{cond}.F32 Sd, Sm
VCMP{E}{cond}.F32 Sd, #0
VCMP{E}{cond}.F64 Dd, Dm
VCMP{E}{cond}.F64 Dd, #0
if present, indicates that the instruction raises an Invalid Operation exception if either operand is a quiet or signaling NaN. Otherwise, it raises the exception only if either operand is a signaling NaN.
is an optional condition code.
Sd, Sm
are the single-precision registers holding the operands.
Dd, Dm
are the double-precision registers holding the operands.


The VCMP{E} instruction subtracts the value in the second operand register (or 0 if the second operand is #0) from the value in the first operand register, and sets the VFP condition flags based on the result.

Floating-point exceptions

VCMP{E} instructions can produce Invalid Operation exceptions.
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