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Assembler User Guide

Preface Overview of the Assembler Overview of the ARM Architecture Structure of Assembly Language Modules Writing ARM Assembly Language Condition Codes Using the Assembler Symbols, Literals, Expressions, and Operators VFP Programming Assembler Command-line Options ARM and Thumb Instructions ARM and Thumb instruction summary Instruction width specifiers Flexible second operand (Operand2) Syntax of Operand2 as a constant Syntax of Operand2 as a register with optional shi Shift operations Saturating instructions Condition code suffixes ADC ADD ADR (PC-relative) ADR (register-relative) ADRL pseudo-instruction AND ASR B BFC BFI BIC BKPT BL BLX BX BXJ CBZ and CBNZ CDP and CDP2 CLREX CLZ CMP and CMN CPS CPY pseudo-instruction DBG DMB DSB EOR ERET HVC ISB IT LDC and LDC2 LDM LDR (immediate offset) LDR (PC-relative) LDR (register offset) LDR (register-relative) LDR pseudo-instruction LDR, unprivileged LDREX LSL LSR MCR and MCR2 MCRR and MCRR2 MLA MLS MOV MOV32 pseudo-instruction MOVT MRC and MRC2 MRRC and MRRC2 MRS (PSR to general-purpose register) MRS (system coprocessor register to ARM register) MSR (ARM register to system coprocessor register) MSR (general-purpose register to PSR) MUL MVN NEG pseudo-instruction NOP ORN (Thumb only) ORR PKHBT and PKHTB PLD and PLI POP PUSH QADD QADD8 QADD16 QASX QDADD QDSUB QSAX QSUB QSUB8 QSUB16 RBIT REV REV16 REVSH RFE ROR RRX RSB RSC SADD8 SADD16 SASX SBC SBFX SDIV SEL SETEND SEV SHADD8 SHADD16 SHASX SHSAX SHSUB8 SHSUB16 SMC SMLAxy SMLAD SMLAL SMLALD SMLALxy SMLAWy SMLSD SMLSLD SMMLA SMMLS SMMUL SMUAD SMULxy SMULL SMULWy SMUSD SRS SSAT SSAT16 SSAX SSUB8 SSUB16 STC and STC2 STM STR (immediate offset) STR (register offset) STR, unprivileged STREX SUB SUBS pc, lr SVC SWP and SWPB SXTAB SXTAB16 SXTAH SXTB SXTB16 SXTH SYS TBB and TBH TEQ TST UADD8 UADD16 UASX UBFX UDIV UHADD8 UHADD16 UHASX UHSAX UHSUB8 UHSUB16 UMAAL UMLAL UMULL UND pseudo-instruction UQADD8 UQADD16 UQASX UQSAX UQSUB8 UQSUB16 USAD8 USADA8 USAT USAT16 USAX USUB8 USUB16 UXTAB UXTAB16 UXTAH UXTB UXTB16 UXTH WFE WFI YIELD VFP Instructions Directives Reference Via File Syntax

STR (immediate offset)

10.133 STR (immediate offset)

Store with immediate offset, pre-indexed immediate offset, or post-indexed immediate offset.


STR{type}{cond} Rt, [Rn {, #offset}] ; immediate offset
STR{type}{cond} Rt, [Rn, #offset]! ; pre-indexed
STR{type}{cond} Rt, [Rn], #offset ; post-indexed
STRD{cond} Rt, Rt2, [Rn {, #offset}] ; immediate offset, doubleword
STRD{cond} Rt, Rt2, [Rn, #offset]! ; pre-indexed, doubleword
STRD{cond} Rt, Rt2, [Rn], #offset ; post-indexed, doubleword
can be any one of:
omitted, for Word.
is an optional condition code.
is the register to store.
is the register on which the memory address is based.
is an offset. If offset is omitted, the address is the contents of Rn.
is the additional register to store for doubleword operations.
Not all options are available in every instruction set and architecture.

Offset ranges and architectures

The following table shows the ranges of offsets and availability of this instruction:

Table 10-15 Offsets and architectures, STR, word, halfword, and byte

Instruction Immediate offset Pre-indexed Post-indexed Arch.
ARM, word or byte –4095 to 4095 –4095 to 4095 –4095 to 4095 All
ARM, halfword –255 to 255 –255 to 255 –255 to 255 All
ARM, doubleword –255 to 255 –255 to 255 –255 to 255 5E
Thumb 32-bit encoding, word, halfword, or byte –255 to 4095 –255 to 255 –255 to 255 T2
Thumb 32-bit encoding, doubleword –1020 to 1020 a –1020 to 1020 a –1020 to 1020 a T2
Thumb 16-bit encoding, word b 0 to 124 a Not available Not available T
Thumb 16-bit encoding, halfword b 0 to 62 d Not available Not available T
Thumb 16-bit encoding, byte b 0 to 31 Not available Not available T
Thumb 16-bit encoding, word, Rn is SP c 0 to 1020 a Not available Not available T

Notes about the Architecture column

Entries in the Architecture column indicate that the instructions are available as follows:
All versions of the ARM architecture.
The ARMv5TE, ARMv6*, and ARMv7 architectures.
The ARMv6T2 and above architectures.
The ARMv4T, ARMv5T*, ARMv6*, and ARMv7 architectures.

Register restrictions

Rn must be different from Rt in the pre-index and post-index forms.

Doubleword register restrictions

Rn must be different from Rt2 in the pre-index and post-index forms.
For Thumb instructions, you must not specify SP or PC for either Rt or Rt2.
For ARM instructions:
  • Rt must be an even-numbered register.
  • Rt must not be LR.
  • ARM strongly recommends that you do not use R12 for Rt.
  • Rt2 must be R(t + 1).

Use of PC

In ARM instructions you can use PC for Rt in STR word instructions and PC for Rn in STR instructions with immediate offset syntax (that is the forms that do not writeback to the Rn). However, this is deprecated in ARMv6T2 and above.
Other uses of PC are not permitted in these ARM instructions.
In Thumb code, using PC in STR instructions is not permitted.

Use of SP

You can use SP for Rn.
In ARM code, you can use SP for Rt in word instructions. You can use SP for Rt in non-word instructions in ARM code but this is deprecated in ARMv6T2 and above.
In Thumb code, you can use SP for Rt in word instructions only. All other use of SP for Rt in this instruction is not permitted in Thumb code.


    STR     r2,[r9,#consta-struc]   ; consta-struc is an expression
                                    ; evaluating to a constant in 
                                    ; the range 0-4095.
Related concepts
Must be divisible by 4.
Rt and Rn must be in the range R0-R7.
Rt must be in the range R0-R7.
Must be divisible by 2.
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