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Assembler User Guide

Preface Overview of the Assembler Overview of the ARM Architecture Structure of Assembly Language Modules Writing ARM Assembly Language Condition Codes Using the Assembler Symbols, Literals, Expressions, and Operators VFP Programming Assembler Command-line Options ARM and Thumb Instructions ARM and Thumb instruction summary Instruction width specifiers Flexible second operand (Operand2) Syntax of Operand2 as a constant Syntax of Operand2 as a register with optional shi Shift operations Saturating instructions Condition code suffixes ADC ADD ADR (PC-relative) ADR (register-relative) ADRL pseudo-instruction AND ASR B BFC BFI BIC BKPT BL BLX BX BXJ CBZ and CBNZ CDP and CDP2 CLREX CLZ CMP and CMN CPS CPY pseudo-instruction DBG DMB DSB EOR ERET HVC ISB IT LDC and LDC2 LDM LDR (immediate offset) LDR (PC-relative) LDR (register offset) LDR (register-relative) LDR pseudo-instruction LDR, unprivileged LDREX LSL LSR MCR and MCR2 MCRR and MCRR2 MLA MLS MOV MOV32 pseudo-instruction MOVT MRC and MRC2 MRRC and MRRC2 MRS (PSR to general-purpose register) MRS (system coprocessor register to ARM register) MSR (ARM register to system coprocessor register) MSR (general-purpose register to PSR) MUL MVN NEG pseudo-instruction NOP ORN (Thumb only) ORR PKHBT and PKHTB PLD and PLI POP PUSH QADD QADD8 QADD16 QASX QDADD QDSUB QSAX QSUB QSUB8 QSUB16 RBIT REV REV16 REVSH RFE ROR RRX RSB RSC SADD8 SADD16 SASX SBC SBFX SDIV SEL SETEND SEV SHADD8 SHADD16 SHASX SHSAX SHSUB8 SHSUB16 SMC SMLAxy SMLAD SMLAL SMLALD SMLALxy SMLAWy SMLSD SMLSLD SMMLA SMMLS SMMUL SMUAD SMULxy SMULL SMULWy SMUSD SRS SSAT SSAT16 SSAX SSUB8 SSUB16 STC and STC2 STM STR (immediate offset) STR (register offset) STR, unprivileged STREX SUB SUBS pc, lr SVC SWP and SWPB SXTAB SXTAB16 SXTAH SXTB SXTB16 SXTH SYS TBB and TBH TEQ TST UADD8 UADD16 UASX UBFX UDIV UHADD8 UHADD16 UHASX UHSAX UHSUB8 UHSUB16 UMAAL UMLAL UMULL UND pseudo-instruction UQADD8 UQADD16 UQASX UQSAX UQSUB8 UQSUB16 USAD8 USADA8 USAT USAT16 USAX USUB8 USUB16 UXTAB UXTAB16 UXTAH UXTB UXTB16 UXTH WFE WFI YIELD VFP Instructions Directives Reference Via File Syntax

LDR (register-relative)

10.45 LDR (register-relative)

Load register. The address is an offset from a base register.


LDR{type}{cond}{.W} Rt, label
LDRD{cond} Rt, Rt2, label ; Doubleword
can be any one of:
unsigned Byte (Zero extend to 32 bits on loads.)
signed Byte (LDR only. Sign extend to 32 bits.)
unsigned Halfword (Zero extend to 32 bits on loads.)
signed Halfword (LDR only. Sign extend to 32 bits.)
omitted, for Word.
is an optional condition code.
is an optional instruction width specifier.
is the register to load or store.
is the second register to load or store.
is a symbol defined by the FIELD directive. label specifies an offset from the base register which is defined using the MAP directive.
label must be within a limited distance of the value in the base register.

Offset range and architectures

The assembler calculates the offset from the base register for you. The assembler generates an error if label is out of range.
The following table shows the possible offsets between the label and the current instruction:

Table 10-13 Register-relative offsets

Instruction Offset range Architectures
ARM LDR, LDRB a +/– 4095 All
ARM LDRD +/– 255 5E
Thumb, 32-bit LDR, LDRB, LDRSB, LDRH, LDRSH a –255 to 4095 T2
Thumb, 32-bit LDRD +/– 1020 b T2
Thumb, 16-bit LDR c 0 to 124 b T
Thumb, 16-bit LDRH c 0 to 62 d T
Thumb, 16-bit LDRB c 0 to 31 T
Thumb, 16-bit LDR, base register is SP e 0 to 1020 b T

Notes about the Architectures column

Entries in the Architectures column indicate that the instructions are available as follows:
All versions of the ARM architecture.
The ARMv5TE, ARMv6*, and ARMv7 architectures.
The ARMv6T2 and above architectures.
The ARMv4T, ARMv5T*, ARMv6*, and ARMv7 architectures.

LDR (register-relative) in Thumb

You can use the .W width specifier to force LDR to generate a 32-bit instruction in Thumb code. LDR.W always generates a 32-bit instruction, even if the target could be reached using a 16-bit LDR.
For forward references, LDR without .W always generates a 16-bit instruction in Thumb code, even if that results in failure for a target that could be reached using a 32-bit Thumb LDR instruction.

Doubleword register restrictions

For 32-bit Thumb instructions, you must not specify SP or PC for either Rt or Rt2.
For ARM instructions:
  • Rt must be an even-numbered register.
  • Rt must not be LR.
  • ARM strongly recommends that you do not use R12 for Rt.
  • Rt2 must be R(t + 1).

Use of PC

You can use PC for Rt in word instructions. Other uses of PC are not permitted in these instructions.

Use of SP

In ARM code, you can use SP for Rt in word instructions. You can use SP for Rt in non-word ARM instructions but this is deprecated in ARMv6T2 and above.
In Thumb code, you can use SP for Rt in word instructions only. All other use of SP for Rt in these instructions are not permitted in Thumb code.
For word loads, Rt can be the PC. A load to the PC causes a branch to the address loaded. In ARMv4, bits[1:0] of the address loaded must be 0b00. In ARMv5T and above, bits[1:0] must not be 0b10, and if bit[0] is 1, execution continues in Thumb state, otherwise execution continues in ARM state.
Must be a multiple of 4.
Rt and base register must be in the range R0-R7.
Must be a multiple of 2.
Rt must be in the range R0-R7.
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