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Assembler User Guide

Preface Overview of the Assembler Overview of the ARM Architecture Structure of Assembly Language Modules Writing ARM Assembly Language Condition Codes Using the Assembler Symbols, Literals, Expressions, and Operators VFP Programming Assembler Command-line Options ARM and Thumb Instructions ARM and Thumb instruction summary Instruction width specifiers Flexible second operand (Operand2) Syntax of Operand2 as a constant Syntax of Operand2 as a register with optional shi Shift operations Saturating instructions Condition code suffixes ADC ADD ADR (PC-relative) ADR (register-relative) ADRL pseudo-instruction AND ASR B BFC BFI BIC BKPT BL BLX BX BXJ CBZ and CBNZ CDP and CDP2 CLREX CLZ CMP and CMN CPS CPY pseudo-instruction DBG DMB DSB EOR ERET HVC ISB IT LDC and LDC2 LDM LDR (immediate offset) LDR (PC-relative) LDR (register offset) LDR (register-relative) LDR pseudo-instruction LDR, unprivileged LDREX LSL LSR MCR and MCR2 MCRR and MCRR2 MLA MLS MOV MOV32 pseudo-instruction MOVT MRC and MRC2 MRRC and MRRC2 MRS (PSR to general-purpose register) MRS (system coprocessor register to ARM register) MSR (ARM register to system coprocessor register) MSR (general-purpose register to PSR) MUL MVN NEG pseudo-instruction NOP ORN (Thumb only) ORR PKHBT and PKHTB PLD and PLI POP PUSH QADD QADD8 QADD16 QASX QDADD QDSUB QSAX QSUB QSUB8 QSUB16 RBIT REV REV16 REVSH RFE ROR RRX RSB RSC SADD8 SADD16 SASX SBC SBFX SDIV SEL SETEND SEV SHADD8 SHADD16 SHASX SHSAX SHSUB8 SHSUB16 SMC SMLAxy SMLAD SMLAL SMLALD SMLALxy SMLAWy SMLSD SMLSLD SMMLA SMMLS SMMUL SMUAD SMULxy SMULL SMULWy SMUSD SRS SSAT SSAT16 SSAX SSUB8 SSUB16 STC and STC2 STM STR (immediate offset) STR (register offset) STR, unprivileged STREX SUB SUBS pc, lr SVC SWP and SWPB SXTAB SXTAB16 SXTAH SXTB SXTB16 SXTH SYS TBB and TBH TEQ TST UADD8 UADD16 UASX UBFX UDIV UHADD8 UHADD16 UHASX UHSAX UHSUB8 UHSUB16 UMAAL UMLAL UMULL UND pseudo-instruction UQADD8 UQADD16 UQASX UQSAX UQSUB8 UQSUB16 USAD8 USADA8 USAT USAT16 USAX USUB8 USUB16 UXTAB UXTAB16 UXTAH UXTB UXTB16 UXTH WFE WFI YIELD VFP Instructions Directives Reference Via File Syntax


10.22 BLX

Branch with Link and exchange instruction set.


BLX{cond}{.W} label
BLX{cond} Rm
is an optional condition code. cond is not available on all forms of this instruction.
is an optional instruction width specifier to force the use of a 32-bit BLX instruction in Thumb.
is a PC-relative expression.
is a register containing an address to branch to.


The BLX instruction causes a branch to label, or to the address contained in Rm. In addition:
  • The BLX instruction copies the address of the next instruction into LR (R14, the link register).
  • The BLX instruction can change the instruction set.
    BLX label always changes the instruction set. It changes a processor in ARM state to Thumb state, or a processor in Thumb state to ARM state.
    BLX Rm derives the target instruction set from bit[0] of Rm:
    • if bit[0] of Rm is 0, the processor changes to, or remains in, ARM state
    • if bit[0] of Rm is 1, the processor changes to, or remains in, Thumb state.

Instruction availability and branch ranges

The following table shows the BLX instructions that are available in ARM and Thumb state. Instructions that are not shown in this table are not available. Notes in brackets show the first architecture version where the instruction is available.

Table 10-7 BLX instruction availability and range

Instruction ARM   Thumb, 16-bit encoding Thumb, 32-bit encoding
BLX label ±32MB (5) ±4MB a (5T) ±16MB (All T2 except ARMv7-M)
BLX Rm Available (5) Available (5T) Use 16-bit (All T2)
BLX{cond} Rm Available (5) -   - -

Register restrictions

You can use PC for Rm in the ARM BLX instruction, but this is deprecated in ARMv6T2 and above. You cannot use PC in other ARM instructions.
You can use PC for Rm in the Thumb BLX instruction. You cannot use PC in other Thumb instructions.
You can use SP for Rm in this ARM instruction but this is deprecated in ARMv6T2 and above.
You can use SP for Rm in the Thumb BLX instruction, but this is deprecated. You cannot use SP in the other Thumb instructions.

Condition flags

This instruction does not change the flags.


See the preceding table for details of availability of the BLX instruction in each architecture.
BLX label and BL label are an instruction pair.
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