Assembler User GuidePreface Overview of the Assembler Overview of the ARM Architecture Structure of Assembly Language Modules Writing ARM Assembly Language Condition Codes Using the Assembler Symbols, Literals, Expressions, and Operators VFP Programming Architecture support for VFP Half-precision extension for VFP Fused Multiply-Add extension for VFP Extension register bank mapping in VFP VFP views of the extension register bank Load values to VFP registers Conditional execution of VFP instructions Floating-point exceptions in VFP VFP data types Extended notation extension for VFP VFP system registers Flush-to-zero mode When to use flush-to-zero mode in VFP The effects of using flush-to-zero mode in VFP VFP operations not affected by flush-to-zero mode VFP vector mode Vectors in the VFP extension register bank VFP vector wrap-around VFP vector stride Restriction on vector length Control of scalar, vector, and mixed operations Overview of VFP directives and vector notation Pre-UAL VFP syntax and mnemonics Vector notation VFPASSERT SCALAR VFPASSERT VECTOR Assembler Command-line Options ARM and Thumb Instructions VFP Instructions Directives Reference Via File Syntax
8.26 VFPASSERT VECTOR
If a function expects VFP to be in vector mode on entry, place a
This directive does not generate any code. It is only an assertion by the programmer. The assembler produces error messages if any such assertions are inconsistent with each other, or with any vector notation in VFP data processing instructions.
VMRS r10,FPSCR ; UAL mnemonic - could be FMRX instead. BIC r10,r10,#0x00370000 ORR r10,r10,#0x00020000 ; set length = 3, stride = 1 VMSR FPSCR,r10 VFPASSERT VECTOR ; assert vector mode, unspecified length ; and stride faddd d4, d4, d0 ; ERROR, scalars in vector mode fadds s16<3>, s8<3>, s0 ; okay fabss s24<1>, s28<1> ; wrong length, but not faulted ; (unspecified) VMRS r10,FPSCR BIC r10,r10,#0x00370000 ORR r10,r10,#0x00030000 ; set length = 4, stride = 1 VMSR FPSCR,r10 VFPASSERT VECTOR<4> ; assert vector mode, length 4, stride 1 fadds s24<4>, s8<4>, s0 ; okay fabss s24<2>, s24<2> ; ERROR, wrong length VMRS r10,FPSCR BIC r10,r10,#0x00370000 ORR r10,r10,#0x00130000 ; set length = 4, stride = 2 VMSR FPSCR,r10 VFPASSERT VECTOR<4:2> ; assert vector mode, length 4, stride 2 fadds s8<4>, s16<4>, s0 ; ERROR, wrong stride because omitting ; stride causes a default stride of 1. fabss s16<4:2>, s28<4:2> ; okay fadds s8<>, s16<>, s2 ; okay (s8 and s16 both have ; length 4 and stride 2. s2 is scalar.)
of your data.