Assembler User GuidePreface Overview of the Assembler Overview of the ARM Architecture Structure of Assembly Language Modules Writing ARM Assembly Language Condition Codes Using the Assembler Symbols, Literals, Expressions, and Operators VFP Programming Architecture support for VFP Half-precision extension for VFP Fused Multiply-Add extension for VFP Extension register bank mapping in VFP VFP views of the extension register bank Load values to VFP registers Conditional execution of VFP instructions Floating-point exceptions in VFP VFP data types Extended notation extension for VFP VFP system registers Flush-to-zero mode When to use flush-to-zero mode in VFP The effects of using flush-to-zero mode in VFP VFP operations not affected by flush-to-zero mode VFP vector mode Vectors in the VFP extension register bank VFP vector wrap-around VFP vector stride Restriction on vector length Control of scalar, vector, and mixed operations Overview of VFP directives and vector notation Pre-UAL VFP syntax and mnemonics Vector notation VFPASSERT SCALAR VFPASSERT VECTOR Assembler Command-line Options ARM and Thumb Instructions VFP Instructions Directives Reference Via File Syntax
Control of scalar, vector, and mixed operations
8.21 Control of scalar, vector, and mixed operations
Whether a VFP arithmetic instruction operates on scalars, vectors, or a mixture of both depends on the LEN bits in the FPSCR and also on which register bank the destination and operand registers are in.
The first bank of registers, s0 to s7 or d0 to d3 and the fifth bank of registers d16 to d19 are scalar banks. All other banks are vector banks. A vector operation or mixed operation is one where the destination register is in one of the vector banks.
Given instructions of the following general forms:
the behavior of the operation is as follows:
In scalar operations,
In vector operations,
In mixed operations, with a single operand,
In mixed operations, with two operands,
of your data.