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Processor modes in ARMv6-M and ARMv7-M
VFP hardware
ARM registers
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Register accesses
Predeclared core register names
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The Q flag
Current Program Status Register
Saved Program Status Registers
ARM and Thumb instruction set overview
Access to the inline barrel shifter
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Writing ARM Assembly Language
Condition Codes
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VFP Programming
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Current Program Status Register
| Non-Confidential |  PDF version | ARM DUI0379H | ||
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| Home > Overview of the ARM Architecture > Current Program Status Register | ||||
2.16 Current Program Status Register
The Current Program Status Register (CPSR) holds the same program status flags as the APSR, and some additional information.
The CPSR holds:
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The APSR flags.
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The processor mode.
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The interrupt disable flags.
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The instruction set state (ARM, Thumb, ThumbEE, or Jazelle®).
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The endianness state (on ARMv4T and later).
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The execution state bits for the IT block (on ARMv6T2 and later).
The execution state bits control conditional execution in the IT block.
Only the APSR flags are accessible in all modes. ARM deprecates using an
MSR instruction to change the endianness bit (E) of the
CPSR, in any mode. SETEND is the preferred instruction to
write to the E bit.The execution state bits for the IT block (IT[1:0]), Jazelle bit (J), and
Thumb bit (T) can be accessed by
MRS only in Debug
state.Note
The CPSR is not present in ARMv6-M and ARMv7-M processors.| Non-Confidential | PDF version | ARM DUI0379H |
| Copyright © 2007, 2008, 2011, 2012, 2014-2016 ARM. All rights reserved. |
| Home > Overview of the ARM Architecture > Current Program Status Register |
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