Keil Logo

C51: Latency of Interrupt Service Routines


Information in this article applies to:

  • C51 Version 4 and Later

QUESTION

What is the interrupt latency of interrupt service routines (ISR) in C51?

ANSWER

There are a number of things that impact how quickly an interrupt is serviced. For example, the following all delay an interrupt:

  • Interrupts disabled (EA = 0)
  • Another interrupt is being processed
  • A higher priority interrupt is being processed

Assuming that interrupts are enabled and that there is no higher priority interrupt that is executing, a new interrupt is serviced by the Microcontroller immediately. Then, the interrupt service routine is entered. For example, the following C interrupt code:

   3          static unsigned counter = 0;
   4
   5          void ISR (void) interrupt 0 using 1
   6          {
   7   1      counter++;
   8   1      }

generates the following assembly code:

0000 C0E0              PUSH    ACC
                                           ; SOURCE LINE # 5
                                           ; SOURCE LINE # 7
0002 0500        R     INC     counter+01H
0004 E500        R     MOV     A,counter+01H
0006 7002              JNZ     ?C0006
0008 0500        R     INC     counter
000A         ?C0006:
                                           ; SOURCE LINE # 8
000A D0E0              POP     ACC
000C 32                RETI

As you can see, there is not a lot of overhead there to retard the performance of your ISRs.

SEE ALSO


Last Reviewed: Thursday, February 25, 2021


Did this article provide the answer you needed?
 
Yes
No
Not Sure
 
  Arm logo
Important information

This site uses cookies to store information on your computer. By continuing to use our site, you consent to our cookies.

Change Settings

Privacy Policy Update

Arm’s Privacy Policy has been updated. By continuing to use our site, you consent to Arm’s Privacy Policy. Please review our Privacy Policy to learn more about our collection, use and transfers
of your data.