CMSIS-Core (Cortex-M)  Version 5.6.0
CMSIS-Core support for Cortex-M processor-based devices
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CMSIS-Core (Cortex-M) implements the basic run-time system for a Cortex-M device and gives the user access to the processor core and the device peripherals. In detail it defines:

  • Hardware Abstraction Layer (HAL) for Cortex-M processor registers with standardized definitions for the SysTick, NVIC, System Control Block registers, MPU registers, FPU registers, and core access functions.
  • System exception names to interface to system exceptions without having compatibility issues.
  • Methods to organize header files that makes it easy to learn new Cortex-M microcontroller products and improve software portability. This includes naming conventions for device-specific interrupts.
  • Methods for system initialization to be used by each MCU vendor. For example, the standardized SystemInit() function is essential for configuring the clock system of the device.
  • Intrinsic functions used to generate CPU instructions that are not supported by standard C functions.
  • A variable to determine the system clock frequency which simplifies the setup the SysTick timer.

The following sections provide details about the CMSIS-Core (Cortex-M):

CMSIS-Core (Cortex-M) in ARM::CMSIS Pack

Files relevant to CMSIS-Core (Cortex-M) are present in the following ARM::CMSIS directories:

File/Folder Content
CMSIS\Documentation\Core This documentation
CMSIS\Core\Include CMSIS-Core (Cortex-M) header files (for example core_cm3.h, core_cmInstr.h, etc.)
Device Arm reference implementations of Cortex-M devices
Device\_Template_Vendor CMSIS-Core Device Templates for extension by silicon vendors

Processor Support

CMSIS supports the complete range of Cortex-M processors and the Armv8-M/v8.1-M architecture including security extensions.

Cortex-M Generic User Guides

The Cortex-M Device Generic User Guides contain the programmers model and detailed information about the core peripherals and are available for:

CMSIS also supports the following Cortex-M processor variants:

  • Cortex-M1 is a processor designed specifically for implementation in FPGAs (Armv6-M architecture).
  • SecurCore SC000 is designed specifically for smartcard and security applications (Armv6-M architecture).
  • SecurCore SC300 is designed specifically for smartcard and security applications (Armv7-M architecture).
  • Cortex-M35P is a temper resistant Cortex-M processor with optional software isolation using TrustZone for Armv8-M.
  • STAR-MC1 is a variant of Armv8-M with TrustZone designed by Arm China.

Armv8-M and Armv8.1-M Architecture

Armv8-M introduces two profiles baseline (for power and area constrained applications) and mainline (full-featured with optional SIMD, floating-point, and co-processor extensions). Both Armv8-M profiles and Armv8.1-M are supported by CMSIS.

The Armv8-M architecture is described in the Armv8-M Architecture Reference Manual.

The Armv8.1-M architecture further extends Armv8-M with Helium (the so called M-Profile Vector Extension (MVE)), as well as further instruction set and debug extensions. More information about Armv8.1-M architecture is available under Arm Helium technology.

Tested and Verified Toolchains

The CMSIS-Core Device Templates supplied by Arm have been tested and verified with the following toolchains:

  • Arm: Arm Compiler 5.06 update 7 (not for Cortex-M23/33/35P/55/85, Armv8-M, Armv8.1-M)
  • Arm: Arm Compiler 6.16
  • Arm: Arm Compiler 6.6.4 (not for Cortex-M0/23/33/35P/55/85, Armv8-M, Armv8.1-M)
  • GNU: GNU Arm Embedded Toolchain 10-2020-q4-major (10.2.1 20201103)
  • IAR: IAR ANSI C/C++ Compiler for Arm