CMSIS-Core (Cortex-M)  Version 5.3.0
CMSIS-Core support for Cortex-M processor-based devices
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CoreDebug_Type Struct Reference

Structure type to access the Core Debug Register (CoreDebug).

Data Fields

__IOM uint32_t DHCSR
 Offset: 0x000 (R/W) Debug Halting Control and Status Register. More...
__OM uint32_t DCRSR
 Offset: 0x004 ( /W) Debug Core Register Selector Register. More...
__IOM uint32_t DCRDR
 Offset: 0x008 (R/W) Debug Core Register Data Register. More...
__IOM uint32_t DEMCR
 Offset: 0x00C (R/W) Debug Exception and Monitor Control Register. More...

Field Documentation

__IOM uint32_t CoreDebug_Type::DCRDR
__OM uint32_t CoreDebug_Type::DCRSR
__IOM uint32_t CoreDebug_Type::DEMCR
__IOM uint32_t CoreDebug_Type::DHCSR