CMSIS-Core (Cortex-M)  Version 5.3.0
CMSIS-Core support for Cortex-M processor-based devices
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Cache Functions (only Cortex-M7)

Functions for Instruction and Data Cache. More...


 I-Cache Functions
 Functions for the instruction cache.
 D-Cache Functions
 Functions for the data cache.


Cortex-M7 processors include a memory system, which includes an optional MPU and Harvard data and instruction cache with ECC. The optional CPU cache has an instruction and data cache with sizes of [0;4;8;16;32;64]KB. Both instruction and data cache RAM can be configured at implementation time to have Error Correcting Code (ECC) to protect the data stored in the memory from errors.

All cache maintenance operations are executed by writing to registers in the memory mapped System Control Space (SCS) region of the internal PPB memory space.

After reset, you must invalidate each cache before enabling it.

The functions are grouped for: