CMSIS-Core (Cortex-A)  Version 1.2.1
CMSIS-Core support for Cortex-A processor-based devices
 All Data Structures Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
GICInterface_Type Struct Reference

Structure type to access the Generic Interrupt Controller Interface (GICC)

Data Fields

__IOM uint32_t CTLR
 Offset: 0x000 (R/W) CPU Interface Control Register. More...
 
__IOM uint32_t PMR
 Offset: 0x004 (R/W) Interrupt Priority Mask Register. More...
 
__IOM uint32_t BPR
 Offset: 0x008 (R/W) Binary Point Register. More...
 
__IM uint32_t IAR
 Offset: 0x00C (R/ ) Interrupt Acknowledge Register. More...
 
__OM uint32_t EOIR
 Offset: 0x010 ( /W) End Of Interrupt Register. More...
 
__IM uint32_t RPR
 Offset: 0x014 (R/ ) Running Priority Register. More...
 
__IM uint32_t HPPIR
 Offset: 0x018 (R/ ) Highest Priority Pending Interrupt Register. More...
 
__IOM uint32_t ABPR
 Offset: 0x01C (R/W) Aliased Binary Point Register. More...
 
__IM uint32_t AIAR
 Offset: 0x020 (R/ ) Aliased Interrupt Acknowledge Register. More...
 
__OM uint32_t AEOIR
 Offset: 0x024 ( /W) Aliased End Of Interrupt Register. More...
 
__IM uint32_t AHPPIR
 Offset: 0x028 (R/ ) Aliased Highest Priority Pending Interrupt Register. More...
 
__IOM uint32_t STATUSR
 Offset: 0x02C (R/W) Error Reporting Status Register, optional. More...
 
__IOM uint32_t APR [4]
 Offset: 0x0D0 (R/W) Active Priority Register. More...
 
__IOM uint32_t NSAPR [4]
 Offset: 0x0E0 (R/W) Non-secure Active Priority Register. More...
 
__IM uint32_t IIDR
 Offset: 0x0FC (R/ ) CPU Interface Identification Register. More...
 
__OM uint32_t DIR
 Offset: 0x1000( /W) Deactivate Interrupt Register. More...
 

Field Documentation

__IOM uint32_t GICInterface_Type::ABPR

CPU Interface Aliased Binary Point Register

See Also
GICInterface_Type::BPR
__OM uint32_t GICInterface_Type::AEOIR

CPU Interface Aliased End Of Interrupt Register

See Also
GICInterface_Type::EOIR
__IM uint32_t GICInterface_Type::AHPPIR

CPU Interface Aliased Highest Priority Pending Interrupt Register

See Also
GICInterface_Type::HPPIR
__IM uint32_t GICInterface_Type::AIAR

CPU Interface Aliased Interrupt Acknowledge Register

See Also
GICInterface_Type::IAR
__IOM uint32_t GICInterface_Type::APR[4]

CPU Interface Active Priorities Registers

Note
The register values are IMPLEMENTATION DEFINED.
__IOM uint32_t GICInterface_Type::BPR

CPU Interface Binary Point Register

Bits Name Function
[31:3] - Reserved.
[2:0] Binary_Point Controls how the 8-bit interrupt priority field is split into a group priority field and a subpriority field.

The binary point (values 0-7) defines the amount of priority bits used as subpriority. Please refer to the section Interrupt prioritization in the Arm Generic Interrupt Controller Architecture Specificaton for details.

__IOM uint32_t GICInterface_Type::CTLR

CPU Interface Control Register

Enables the signaling of interrupts by the CPU interface to the connected processor, and provides additional top-level control of the CPU interface. In a GICv2 implementation, this includes control of the end of interrupt (EOI) behavior.

Bits Name Function
[31:1] - Reserved.
[0] Enable Interrupt signaling: 0 - Disable. 1 - Enable.
__OM uint32_t GICInterface_Type::DIR

CPU Interface Deactivate Interrupt Register

Bits Name Function
[31:24] - Reserved.
[23:0] INTID The INTID of the interrupt to be disabled.
__OM uint32_t GICInterface_Type::EOIR

CPU Interface End Of Interrupt Register

Bits Name Function
[31:24] - Reserved.
[23:0] INTID The interrupt number of the finished interrupt.
__IM uint32_t GICInterface_Type::HPPIR

CPU Interface Highest Priority Pending Interrupt Register

Bits Name Function
[31:24] - Reserved.
[23:0] INTID The INTID of the signaled interrupt.
__IM uint32_t GICInterface_Type::IAR

CPU Interface Interrupt Acknowledge Register

Bits Name Function
[31:24] - Reserved.
[23:0] INTID The interrupt number of the signaled interrupt.
__IM uint32_t GICInterface_Type::IIDR

CPU Interface Identification Register

Bits Name Function
[31:20] ProductID An IMPLEMENTATION DEFINED product identifier
[19:16] Arch_version The version of the GIC architecture that is implemented.
[15:12] Revision An IMPLEMENTATION DEFINED revision number for the CPU interface.
[11:0] Implementer Contains the JEP106 code of the company that implemented the CPU interface.
__IOM uint32_t GICInterface_Type::NSAPR[4]

CPU Interface Non-secure Active Priorities Registers

Note
The register values are IMPLEMENTATION DEFINED.
See Also
GICInterface_Type::APR[4]
__IOM uint32_t GICInterface_Type::PMR

CPU Interface Priority Mask Register

Bits Name Function
[31:8] - Reserved.
[7:0] Priority The priority mask level for the CPU interface.
Note
IMPLEMENTATION DEFINED unsupported priority bits might be RAZ/WI.
__IM uint32_t GICInterface_Type::RPR

CPU Interface Running Priority Register

Bits Name Function
[31:8] - Reserved.
[7:0] Priority The current running priority on the CPU interface.
__IOM uint32_t GICInterface_Type::STATUSR

CPU Interface Status Register

Bits Name Function
[31:5] - Reserved.
[4] ASV Attempted security violation.
[3] WROD Write to an RO location.
[2] RWOD Read of a WO location.
[1] WRD Write to a reserved location.
[0] RRD Read of a reserved location.