CMSIS-Core (Cortex-M)  Version 5.6.0
CMSIS-Core support for Cortex-M processor-based devices
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PMU_Type Struct Reference

Structure type to access the Performance Monitoring Unit (PMU). More...

Data Fields

 PMU Event Counter Registers. More...
__IOM uint32_t CCNTR
 PMU Cycle Counter Register. More...
 PMU Event Type and Filter Registers. More...
__IOM uint32_t CCFILTR
 PMU Cycle Counter Filter Register. More...
__IOM uint32_t CNTENSET
 PMU Count Enable Set Register. More...
__IOM uint32_t CNTENCLR
 PMU Count Enable Clear Register. More...
__IOM uint32_t INTENSET
 PMU Interrupt Enable Set Register. More...
__IOM uint32_t INTENCLR
 PMU Interrupt Enable Clear Register. More...
__IOM uint32_t OVSCLR
 PMU Overflow Flag Status Clear Register. More...
__IOM uint32_t SWINC
 PMU Software Increment Register. More...
__IOM uint32_t OVSSET
 PMU Overflow Flag Status Set Register. More...
__IOM uint32_t TYPE
 PMU Type Register. More...
__IOM uint32_t CTRL
 PMU Control Register. More...
 PMU Authentication Status Register. More...
__IOM uint32_t DEVARCH
 PMU Device Architecture Register. More...
__IOM uint32_t DEVTYPE
 PMU Device Type Register. More...
__IOM uint32_t PIDR4
 PMU Peripheral Identification Register 4. More...
__IOM uint32_t PIDR0
 PMU Peripheral Identification Register 0. More...
__IOM uint32_t PIDR1
 PMU Peripheral Identification Register 1. More...
__IOM uint32_t PIDR2
 PMU Peripheral Identification Register 2. More...
__IOM uint32_t PIDR3
 PMU Peripheral Identification Register 3. More...
__IOM uint32_t CIDR0
 PMU Component Identification Register 0. More...
__IOM uint32_t CIDR1
 PMU Component Identification Register 1. More...
__IOM uint32_t CIDR2
 PMU Component Identification Register 2. More...
__IOM uint32_t CIDR3
 PMU Component Identification Register 3. More...


Structure type to access the Performance Monitoring Unit (PMU).

Field Documentation

__IOM uint32_t PMU_Type::AUTHSTATUS

PMU Authentication Status Register.

Offset: 0xFB8 (R/W)

__IOM uint32_t PMU_Type::CCFILTR

PMU Cycle Counter Filter Register.

Offset: 0x47C (R/W)

__IOM uint32_t PMU_Type::CCNTR

PMU Cycle Counter Register.

Offset: 0x7C (R/W)

__IOM uint32_t PMU_Type::CIDR0

PMU Component Identification Register 0.

Offset: 0xFF0 (R/W)

__IOM uint32_t PMU_Type::CIDR1

PMU Component Identification Register 1.

Offset: 0xFF4 (R/W)

__IOM uint32_t PMU_Type::CIDR2

PMU Component Identification Register 2.

Offset: 0xFF8 (R/W)

__IOM uint32_t PMU_Type::CIDR3

PMU Component Identification Register 3.

Offset: 0xFFC (R/W)

__IOM uint32_t PMU_Type::CNTENCLR

PMU Count Enable Clear Register.

Offset: 0xC20 (R/W)

__IOM uint32_t PMU_Type::CNTENSET

PMU Count Enable Set Register.

Offset: 0xC00 (R/W)

__IOM uint32_t PMU_Type::CTRL

PMU Control Register.

Offset: 0xE04 (R/W)

__IOM uint32_t PMU_Type::DEVARCH

PMU Device Architecture Register.

Offset: 0xFBC (R/W)

__IOM uint32_t PMU_Type::DEVTYPE

PMU Device Type Register.

Offset: 0xFCC (R/W)


PMU Event Counter Registers.

Offset: 0x0 (R/W)

Two up to 31 event counters, see device specific __PMU_NUM_EVENTCNT


PMU Event Type and Filter Registers.

Offset: 0x400 (R/W)

Two up to 31 event counters, see device specific __PMU_NUM_EVENTCNT

__IOM uint32_t PMU_Type::INTENCLR

PMU Interrupt Enable Clear Register.

Offset: 0xC60 (R/W)

__IOM uint32_t PMU_Type::INTENSET

PMU Interrupt Enable Set Register.

Offset: 0xC40 (R/W)

__IOM uint32_t PMU_Type::OVSCLR

PMU Overflow Flag Status Clear Register.

Offset: 0xC80 (R/W)

__IOM uint32_t PMU_Type::OVSSET

PMU Overflow Flag Status Set Register.

Offset: 0xCC0 (R/W)

__IOM uint32_t PMU_Type::PIDR0

PMU Peripheral Identification Register 0.

Offset: 0xFE0 (R/W)

__IOM uint32_t PMU_Type::PIDR1

PMU Peripheral Identification Register 1.

Offset: 0xFE4 (R/W)

__IOM uint32_t PMU_Type::PIDR2

PMU Peripheral Identification Register 2.

Offset: 0xFE8 (R/W)

__IOM uint32_t PMU_Type::PIDR3

PMU Peripheral Identification Register 3.

Offset: 0xFEC (R/W)

__IOM uint32_t PMU_Type::PIDR4

PMU Peripheral Identification Register 4.

Offset: 0xFD0 (R/W)

__IOM uint32_t PMU_Type::SWINC

PMU Software Increment Register.

Offset: 0xCA0 (R/W)

__IOM uint32_t PMU_Type::TYPE

PMU Type Register.

Offset: 0xE00 (R/W)